Designing and Optimizing of Sigma-Delta Modulator Using PSO Algorithm

The envelope pulse-width modulation (EPWM) transmitter has been studied to address the power efficiency issue on the linear amplification of OFDM signals. However, the delta- sigma (Delta-Sigma) modulator in the EPWM transmitter generates quantization noise that degrades signal quality. In this paper, OFDM in-band noise characteristics of EPWM transmitters are analyzed for first and second order Delta-Sigma modulators. Distortion noise power due to envelope clipping of OFDM signals is also analyzed. The combined effects of noise and distortion on the error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR) are examined. Simulations to validate the total performance were performed using the IEEE 802.11a OFDM signal. Results showed good agreement with analytical results considering a linear-approximation gain for the 1-bit quantizer in Delta-Sigma modulators. The first order EPWM transmitter provides slightly better EVM and ACLR values than second order EPWM transmitters, since the effective quantizer gain of second order Delta-Sigma modulators is smaller, that limits the noise- shaping capability of Delta-Sigma modulators. A 0.1% clipping probability for a first order EPWM transmitter with an oversampling ratio of 32 and a three-pole Butterworth bandpass filter gives an EVM of 1.8% and ACLR of-37.9 dB.

Sigma delta modulation is a popular technique for high-resolution analog-to-digital conversion and digital-to-analog conversion. We investigate chaotic phenomena in multibit first-order sigma-delta modulators. Particular attention is placed on the occurrence of periodic orbits or limit cycles. These may result in idle tones audible to the listener when sigma-delta modulation is used for audio signal processing. One suggested method of eliminating idle tones is the operation of a sigma delta modulator in the chaotic regime. Unfortunately, chaotic modulation of a first order sigma delta modulator is a poor system for signal processing. We show that minor variations on a traditional first order sigma-delta modulator, together with a multibit implementation, may be used to produce an effective, stable chaotic modulator that accurately encodes the input and helps remove the presence of idle tones. (c) 2001 American Institute of Physics.

A novel third order delta sigma modulator (DSM) is presented. The third order loop filter in the proposed DSM shares one opamp among three integrator stages through an optimal operation timing, which makes use of load capacitance differences between integrator stages. The power dissipation of the proposed DSM is much lower than conventional third order DSM because power consuming blocks in the DSM are only one opamp and a comparator. The proposed DSM, designed on 0.35µm CMOS process under 3.3V supply achieves 1mW power dissipation with 100-11kHz band width and 96dB SQNR.

We present a globally stable arbitrary-order single-bit delta-sigma modulator architecture with continuous-time loop filtering. Using Lyapunov arguments and the method of equivalent control, it is shown that stability is guaranteed for any input signal with peak magnitude less than L>0, where -L and +L denote the quantization levels. The design augments the conventional delta-sigma modulator with switching feedback and the use of distinct operating modes; the additional circuitry required for the implementation of these stabilizing measures is nominal. For a given noise transfer function and fixed oversampling ratio, the new architecture achieves the same peak signal-to-noise-plus-distortion ratio as a traditional delta-sigma modulator. The proposed design can also yield near-peak performance for inputs which destabilize the conventional delta-sigma data converter. Simulation results are provided for the proposed modulator and a comparable standard interpolative design.

Frequency delta-sigma modulator (FDSM) employing a variable frequency oscillator is a novel replacement of the classical delta-sigma modulators. This is advantageous for application to sensors, because an ADC can be intrinsically integrated with the sensors. We have already proposed to use this technique to various sensors. However, the signal-to-noise ratio was significantly degraded by noise floor, in the previous papers. In this paper, we have investigated the origin of the noise floor in the FDSM microphone sensors as a promising example. It was demonstrated that improving the phase noise of the oscillator can drastically reduce the noise floor. For this reduction we improved the Q-factor of the cavity resonator, and the design of the oscillator circuit. With these improvements, the phase noise, and, hence, the noise floor, were improved by approximately 40 dB. In addition, we obtained an SNR of 57 dB for 114 dBSPL sound input with 96 kHz bandwidth, which corresponds to the dynamic range of 87 dB for maximum 140 dBSPL. A much larger dynamic range of around 120 dB is expected by increasing the sampling rate and decreasing the Al diaphragm thickness. These results also indicate the promise of the FDSM to varieties of physical sensors.

This paper presents a continuous-time (CT) delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator was fabricated in a 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m}$ </tex-math></inline-formula> CMOS process with an active area of 0.08 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {mm}^{2}$ </tex-math></inline-formula> . It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2 V power supply.

A digital hardware implementation of Radial Basis Function Neural Network (RBFNN) based on sigma-delta modulated bit-streams is presented. Through the change of feedback coefficient in the framework of traditional sigma-delta modulator, a new limiting amplifier modulator (LAM) is fabricated, and the approximation to Gauss kernel function can be achieved by the combination of several LAMs with different coefficients. The bit-stream neurons with Gauss kernel function and a whole feed-forward artificial neural network is implemented on field programmable gate array (FPGA). Thus a nonlinear function approximation problem can be solved by the neural networks presented.

Although delta-sigma modulators are widely used for low to moderate rate analog-to-digital conversion, the time over-sampling requirement has limited their application to higher rate converters. This paper presents an architecture wherein multiple delta-sigma modulators are combined with time interlacing. Instead, the system achieves the effect of over-sampling from the multiplicity of delta-sigma modulators. For a system containing M Lth order delta-sigma modulators, approximately L bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of robustness of the individual delta-sigma modulators to non-ideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. Because of parallelism, the performance of the architecture is hugely degraded by channel mismatches. A digital technique is used to overcome this problem. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.

There is developed the simulation model of single bit third order sigma-delta modulator. It provides investigation of the influence of components' parameters on modulator's error. It is presented results of investigation of integrator's nonlinearity on integral nonlinearity of this modulator. The presented results provides purposeful selecting of correction function for correction nonlinear error of analog to digital converters based on presented modulator. Also the proposed methodology provides opportunity of parametric optimization in development of sigma-delta modulators.

An architecture for a second-order Sigma Delta modulator is proposed. It is part of an ongoing analysis of the stability of multiloop modulators. This modulator features an increased number of parameters, allowing a designer to swap an increase in stability for a reduction in the signal-to-noise ratio (SNR) for small inputs. The tradeoff, compared to a traditional modulator, is an increase in the complexity of the integrator closest to the comparator. Simulation results are presented that demonstrate the ability to design modulators with superior stability compared to a standard second-order modulator and the ability to design modulators with superior SNR performance over most of the input amplitude range compared to a standard second-order modulator. >

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

Sigma-delta ACD has two main parts: analog modulator and digital filter, the performance of modulator determines the performance of sigma-delta ADC, so the design of modulator is very important. The paper introduces the principle of sigma-delta AD modulator with high accuracy and the applied over sampling technique, noise shaping technique and multi-bit quantizer technique. Determining the design scheme of modulator—three bits three orders CIFF(Cascade of integrators, feed forward form) structure, and it makes the behavior level verification for this scheme by Simulink tool in MATLAB. The simulation result shows that multi-bit quantizer modulator can get very high SNR, and based on this result it designs every part of the modulator circuit.

Objective. The mainstream development trend in the era of intelligent sports. At present, with the rapid development of science and technology, it is absolutely wise to combine group intelligence with community intelligent sports services for the elderly. Group intelligence has opened a new era of intelligent sports service. Group intelligence has become an important factor in the development and growth of community intelligent sports service for the elderly and has become a hot topic at present. However, intelligence has encountered difficulties on the road of development. At present, the aging of the population is getting worse and worse, and the elderly have higher and higher requirements for fitness and leisure services, which leads to the need for sports services to be continuously strengthened. The distribution of resources is uneven, the data is not clear enough, and the swarm intelligence algorithm is not perfect. With the adaptation of the elderly to intelligence, more intelligent, concise, and personalized services need to be developed. The most important method is to optimize the swarm intelligence algorithm continuously. In this paper, PSO algorithm is optimized and HCSSPSO algorithm is proposed. HCSSPSO algorithm is a combination of PSO algorithm and clonal selection strategy, and test simulation experiments, PSO algorithm, CLPSO algorithm, and HCSSPSO algorithm for comparison. From the experimental results, HCSSPSO algorithm has better convergence speed and stability, whether it is data or comparison graph. The data optimized by HCSSPSO algorithm is higher than the original data and the other two algorithms in terms of satisfaction and resource allocation.

This paper demonstrates the effectiveness and robustness of amplifier finite gain bandwidth compensation within a wideband third order continuous time delta sigma modulator and the effects of process, mismatch and temperature on modulator stability. In many state of the art designs, GBW is kept safely above the sampling frequency of the modulator, which suffers a power penalty especially for high-speed designs. While gain errors and phase shifts in the loop filter due to finite GBW can be compensated for, its robustness is often questionable, especially if an additional excess loop delay is concerned. The robustness of such a compensation is analyzed for an exemplary CT DSM with an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> of 500MHz which has been designed in a 1.2V 90nm TSMC CMOS process. Therefore, the amplifiers are compensated for finite GBW values of 500 MHz, 300MHz and 600 MHz, and all three parasitic extracted amplifiers are analyzed over PVT. The simulated modulator performance of 72 dB SNDR over a 25MHz bandwidth is only degraded by 2 dB over corner simulations. In comparison to Monte Carlo analysis of all amplifiers, this reveals a modulator robustness to amplifier finite GBW as much as ±35% over process and mismatch, which emphasizes the feasibility of the approach.

The author discusses multistage modulators, digital processing of pulse density modulation signals, algorithms, testing, modeling nonidealities and stability. Diagrams are given for: an N/sup th/ order sigma delta modulator, a multistage closed loop modulator, a first order digital sigma delta modulator, and a low pass digital comb filter.