An interleaved delta-sigma analog to digital converter with digital correction

The envelope pulse-width modulation (EPWM) transmitter has been studied to address the power efficiency issue on the linear amplification of OFDM signals. However, the delta- sigma (Delta-Sigma) modulator in the EPWM transmitter generates quantization noise that degrades signal quality. In this paper, OFDM in-band noise characteristics of EPWM transmitters are analyzed for first and second order Delta-Sigma modulators. Distortion noise power due to envelope clipping of OFDM signals is also analyzed. The combined effects of noise and distortion on the error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR) are examined. Simulations to validate the total performance were performed using the IEEE 802.11a OFDM signal. Results showed good agreement with analytical results considering a linear-approximation gain for the 1-bit quantizer in Delta-Sigma modulators. The first order EPWM transmitter provides slightly better EVM and ACLR values than second order EPWM transmitters, since the effective quantizer gain of second order Delta-Sigma modulators is smaller, that limits the noise- shaping capability of Delta-Sigma modulators. A 0.1% clipping probability for a first order EPWM transmitter with an oversampling ratio of 32 and a three-pole Butterworth bandpass filter gives an EVM of 1.8% and ACLR of-37.9 dB.

Sigma delta modulation is a popular technique for high-resolution analog-to-digital conversion and digital-to-analog conversion. We investigate chaotic phenomena in multibit first-order sigma-delta modulators. Particular attention is placed on the occurrence of periodic orbits or limit cycles. These may result in idle tones audible to the listener when sigma-delta modulation is used for audio signal processing. One suggested method of eliminating idle tones is the operation of a sigma delta modulator in the chaotic regime. Unfortunately, chaotic modulation of a first order sigma delta modulator is a poor system for signal processing. We show that minor variations on a traditional first order sigma-delta modulator, together with a multibit implementation, may be used to produce an effective, stable chaotic modulator that accurately encodes the input and helps remove the presence of idle tones. (c) 2001 American Institute of Physics.

A digital adaptive calibration technique to linearize sigma-delta (ΣΔ) modulators based on an output-referred distortion analysis of discrete-time integrators (DTIs) is presented. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a DTI, which entails the application of adaptive polynomial transversal filtering for error correction of the modulator. Error-parameter identification is accomplished by correlating various moments of the digital output with a 1-bit pseudorandom noise, which is injected into the analog input of each DTI of the modulator. Simulations demonstrate the effectiveness of the technique in compensating the signal-dependent errors of first- and second-order ΣΔ modulators.

A novel third order delta sigma modulator (DSM) is presented. The third order loop filter in the proposed DSM shares one opamp among three integrator stages through an optimal operation timing, which makes use of load capacitance differences between integrator stages. The power dissipation of the proposed DSM is much lower than conventional third order DSM because power consuming blocks in the DSM are only one opamp and a comparator. The proposed DSM, designed on 0.35µm CMOS process under 3.3V supply achieves 1mW power dissipation with 100-11kHz band width and 96dB SQNR.

A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous‐time delta–sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer‐coded truncation is achieved by re‐ordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital‐to‐analogue converter is simple, and it only introduces a small ELD.

Nonlinear voltage distortion of the inverter affects the control performance of an AC drive, especially during low speed operations. For implementing advanced control algorithm such as sensorless control, compensation of the nonlinearity of the inverter is crucial. Thus, the availability of precise phase voltage measurement has great advantages. However, because of the switching nature of the PWM phase voltages, accurate phase voltage sensing is not trivial. In this paper, a novel direct measurement of the PWM phase voltages for a PMSM drive is introduced. The proposed method combines oversampling based on delta-sigma modulation and digital filtering. The implementation of the approach is based on high speed ADC and FPGA, actually well-known from current measurement and adapted to voltage measurement in this paper. The effectiveness and reliability of the proposed method are verified with experimental results.

A self-adaptive Sigma-Delta modulator, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance, is presented in this paper. Traditional Sigma-Delta modulator mainly focused on using a 2nd order sensing element to improve the SNR, whereas this paper presents a 5th order Sigma-Delta modulator to obtain higher SNR. Specifically, an additional 3rd order digital loop integrator is inserted between the AFE and the quantizer, which increases overall loop order to produce much higher SNR for Sigma-Delta modulator and the parameters of the 3rd order digital loop integrator are optimized by swarm intelligent algorithm. Simulation results with respect to the proposed 5th order Sigma-Delta modulator, SNR >122 dB and the noise floor under -170dB are obtained in frequency range of [5-150Hz]. In further simulation, the robustness of the proposed 5th order Sigma-Delta modulator is analyzed.

Delta Sigma Analog to Digital Converters (ADCs) are superior to their counterparts in achieving high resolution for low to medium bandwidth applications. This paper discusses an improved digital calibration technique for enhancing Signal to Noise ratio (SNR) of Delta Sigma ADC which is directly related to Effective Number of Bits (ENOB). The proposed method uses the Adaptive Line Enhancer (ALE) for improving the SNR of the modulator. Adaptive Line Enhancer filters out the estimate of signal of interest from noisy input signal by updating filter coefficients using Least Mean Square (LMS) Algorithm. Variable step size (VSS) LMS is used for updating filter coefficients in Adaptive Line Enhancer instead of Fixed step size (FSS) LMS to reduce the required number of iterations. The simulation results for second order single loop Delta Sigma modulator show approximately 20dB improvement in SNR after calibration and substitution of VSS LMS with FSS LMS has reduced approximately 4000 iterations.

There is developed the simulation model of single bit third order sigma-delta modulator. It provides investigation of the influence of components' parameters on modulator's error. It is presented results of investigation of integrator's nonlinearity on integral nonlinearity of this modulator. The presented results provides purposeful selecting of correction function for correction nonlinear error of analog to digital converters based on presented modulator. Also the proposed methodology provides opportunity of parametric optimization in development of sigma-delta modulators.

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

Low power, high resolution and high-speed ADCs are becoming increasingly important with advancements in portable electronics, from mobile phones and pagers to CD players and MP3 players. This is certainly not feasible on a handheld device which is why new ADC techniques must be developed. They are becoming increasingly attractive to major data converter manufacturers and their designers because pipeline ADCs provide an optimal balance of scale, speed, resolution, power dissipation and analogue design effort. Because of latency and errors in comparators & gain stages in pipelined ADCs, the need arises for digital error correction mechanism. The digital error correction logic will be implemented for 8-bit ADC using 1.5 bits per stage. While designing we are considering important parameters of CMOS like propagation delay performance and power dissipation. The VLSI realization of digital arithmetic is implemented using TANNER EDA software tool using 0.18µm CMOS process.

A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer

An architecture for a second-order Sigma Delta modulator is proposed. It is part of an ongoing analysis of the stability of multiloop modulators. This modulator features an increased number of parameters, allowing a designer to swap an increase in stability for a reduction in the signal-to-noise ratio (SNR) for small inputs. The tradeoff, compared to a traditional modulator, is an increase in the complexity of the integrator closest to the comparator. Simulation results are presented that demonstrate the ability to design modulators with superior stability compared to a standard second-order modulator and the ability to design modulators with superior SNR performance over most of the input amplitude range compared to a standard second-order modulator. >

The author discusses multistage modulators, digital processing of pulse density modulation signals, algorithms, testing, modeling nonidealities and stability. Diagrams are given for: an N/sup th/ order sigma delta modulator, a multistage closed loop modulator, a first order digital sigma delta modulator, and a low pass digital comb filter.

This paper presents a precision wide range Delta Sigma ADC SC1601 (SC1601 is the product number of ADC) with programmable gain amplifier (PGA) and programmable output data rate features. The ADC offers four fully differential input channels. Each channel can be programmed with a gain of 1 to 128 in binary steps i.e. in powers of 2. The ADC uses a second order delta sigma modulator (DSM) followed by a digital sinc\(^3\) filter. The output data rate of the ADC is also programmable from 312.5 Hz to 2.5 kHz either to achieve higher accuracy or higher speed. The ADC also offers on chip offset and gain calibration features to reduce the offset and gain errors. The serial interface of ADC is SPI\(^{TM}\) compatible. The SC1601 ADC is fabricated in 0.18 \(\upmu \)m CMOS process at Semi-Conductor Laboratory (SCL). The total power consumption of the ADC is 4 mW and it consumes total silicon area of 2.25 mm\(^2\). SC1601 ADC achieves a maximum ENOB of 19.15 bits at a data rate of 312.5 Hz with a full scale range of 1.22 V. The ADC requires a supply voltage of 3.3 V and 1.8 V and can operate in a wide temperature range of −55\(^{\circ }\)C to 125\(^{\circ }\)C. SC1601 ADC is developed for the satellite launch vehicle telemetry system.KeywordsDelta sigma modulatorAnalog multiplexerProgrammable gain amplifierDigital filter