A new approach on power estimation of CMOS sequential logic circuits

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

A study is made of single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this article, we propose a novel model checking-based methodology that analyzes the hardware trojan (HT)-based security vulnerabilities in sequential circuits with 100% coverage while addressing the state-space explosion issue and completeness issue. In this work, the state-space explosion issue is addressed by efficiently partitioning the larger state space into corresponding smaller state spaces to enable the distributed HT-based security analysis of complex sequential circuits. We analyze multiple ISCAS89 and trust-hub benchmarks for different ASIC technologies, i.e., 65, 45, and 22 nm, to demonstrate the efficacy of our framework in identifying HT-based security vulnerabilities. The experimental results show that ForASec successfully performs the complete analysis of the given complex and large sequential circuits, and provides approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> speedup in analysis time compared to the state-of-the-art model checking-based techniques.

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

Logic circuits in digital electronics can generally be classified two categories-combinational and sequential logic circuits.There are several software-based applications and hardware description languages to describe the structure and behavior of electronic circuits.Although it is an easy to construct a state transition table from the state transition diagram,creating an excitation table according to the memory element type in the sequential circuit design is a very laborious and time-consuming task.After the logic functions extracted from the state transition tables are obtained,logic design verification can be carried out by a conventional simulator.This will require time and persistence much like learning any other skill.Computer science degrees include courses focused mainly on programming languages.There’s a strong case to be made for use of skills acquired in programming courses to shorten the learning curve.Thus, this work has proposed a method for the implementation of the circuit only the state equations of the sequential circuit without dealing with excitation tables.This eliminates the process of constructing the circuit schematically, since it does not require flip-flop selection.In this method, since the state equations can be expressed through buttonbox,checkbox,textbox etc.which are the basic elements of the programming language,the behavior of the circuit can be observed in a very short time.

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. (1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. (2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. (3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. (4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.

Due to the rapid advancements in semiconductor production, increasing design complexity, and the need for gigahertz operating frequencies, designing VLSI circuits digitally presents several obstacles. Keeping power dissipation within reasonable bounds is one of the main issues designers face. The necessity for portable electronics, the shrinking transistor sizes, and the growing number of devices per chip all contribute to rising power consumption. The design and verification of very large-scale integration (VLSI) circuits depend heavily on this issue. Therefore, minimizing power dissipation throughout the design phase is crucial and requires precise power dissipation estimation. This enables the prevention of expensive and highly complex redesigns that might emerge due to violation of the power constraint. This paper presents a power estimation technique based on the backpropagation neural networks for estimating power consumption of the combinational and sequential circuits. In the proposed method, mean square error and regression analysis are used for measuring the deviations between the actual power and estimated power obtained by SPICE/Monte Carlo simulation. The deviations from the ideal power estimator using BPNN are found to be approximately 0.77% for NAND-based and 1.04% for NOR-based combinational circuits, and around 0.01% for sequential circuits. The MSE for NAND and NOR combinational circuits is 0.88751 and 1.08402, respectively, while for sequential circuits, it is approximately 6.254 × 10−5. These results demonstrate that the BPNN-based method provides highly accurate power estimation.

Abstract: In this paper, we present a Monte Carlo based technique to estimate signal activity at the internal nodes of sequential logic circuits. The technique takes spatial and temporal correlations of logic signals into consideration. The Monte Carlo based techniques that have been proposed for combinational circuits can not be directly applied to sequential circuits due to the initial transient problem. The proposed approach deals with this problem by gaining insight from Markov chain theory. Experimental results show that the error (%) of estimated activity of individual nodes is within 3% in comparison to that of long run simulation results.

Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verification (PFV) techniques are being explored, as they provide guaranteed polynomial upper bounds on the time and space required for the verification process. Recently, it was shown that circuits characterized by a constant cutwidth can be verified in linear time using Answer Set Programming (ASP). However, these results are limited to combinational circuits, whereas most designs used in digital systems are sequential. In this paper, we introduce Linear Formal Verification (LFV) as a subclass of PFV for sequential circuits with constant cutwidth, which are verifiable in linear time and space using ASP. We achieve this by proposing a new data structure called Weighted And-Inverter Graph (W-AIG). Unlike existing formal verification methods, we prove that our approach can verify any sequential circuit with a constant cutwidth in linear time and space. Finally, we implement our approach and experimentally show that a variety of sequential circuits, such as pipelined adders, serial adders, and shift registers, can be verified in linear time and space, while ring counters can be verified in polynomial time and space, confirming our theoretical findings.

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.

The advantage of Evolvable Hardware over the traditional circuit design approach is its capacity for dynamic and autonomous adaptation. EHW can reconfigure its structure according to changes in the task requirement or the environment in which the EHW is embedded. Focuses on the application of extrinsic evolution and their used for the design of small sequential circuits. At the foundation of evolvable hardware, a full-connected feed-forward circuit network model was constructed which is based on the character of sequential circuits. This model is imitating the structure of artificial neural network. It firstly using D flip-latch and logic gate as the basic element, and the one-to-one mapping existed in the mathematical encoding, circuit topology, and HDL file was established. Then, the method to obtain HDL file according to circuit encoding was designed, the circuit evaluation process was automated by using of batch processing technology. Designed the mutation rate dynamic adjust function to improve the performance of (1+λ)-ES. Experiment results of two types of Finite State Machine proved the feasibility and validity of the circuit evolution method.

In signature analysis, aliasing is usually examined under the independent or the q-ary symmetric error model. In contrast to the independent error model, the q-ary error model assumes space correlation among outputs. However, both independent and q-ary error models assume that the errors resulting from consecutive test vectors are independent over time. This assumption is reasonable for combinational circuits but certainly unrealistic for sequential logic circuits as the outputs of a sequential circuit depend on the previous state as well as the current input vector. For this reason a new error model, called the generalised time dependent q-ary (GTDQ) error model, is proposed. This error model extends the q-ary error model to consider both space and time correlation. A second parameter c is used to model the time correlation. By modelling the signature analyser as a Markov process the authors obtain a closed form expression for exact aliasing probability for arbitrary test length for a class of multiple-input linear automata signature registers (MILASRs). An easily verifiable criterion is given to determine whether a MILASR falls into this category. Finally, experimental results are provided for some real sequential circuits to validate the proposed error models.

Optimizing power dissipation is now a major concern in IC design. Accurate power estimation at the circuit level is too expensive. Tools which estimate power dissipation at higher levels of abstraction without sacrificing accuracy are of interest. We discuss a new cell-library based technique for power estimation. An I/O transition model is developed to represent energy consumption in library elements. Power estimation based on the I/O model requires less computational effort than with previous models. The I/O model also addresses accuracy limitation of previous models. A power estimation tool IOTA, based on this model, has been implemented in C and Matlab. For reasonably large combinational and sequential arithmetic circuits, IOTA has an average error of 5% and low simulation time compared to SPICE simulations.

We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which has been extended to handle temporal correlation and arbitrary transport delays. The method can target both combinational and sequential circuits. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. When l = L, where L is the total number of levels of logic in the circuit, the method will produce the exact switching activity under a zero delay model, taking into account all internal correlation. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples, power estimates with l = 0 are within 5% of the exact. However, this error can be higher than 20% for some examples. More robust estimates are obtained with l = 2, providing a good compromise between speed and accuracy.