Linear Formal Verification of Sequential Circuits using Weighted-AIGs

INSTEP is a satisfiability checker designed for the original purpose of solving a specific target set of problems in the formal verification of VLSI circuits. These are real-world problems concerning a sequential circuit that is part of a commercial chip manufactured by Texas Instruments. The program has succeeded in solving these problems, which require satisfiability checking for combinational representations containing up to around 10 000 variables and a graphical representation of around 17 000 nodes. It has also been successfully applied to a number of standard benchmark problems in combinational circuit verification. Results on these benchmarks are overall competitive with those for the widely used method based onbinary decision diagrams, and for the first time demonstrate the solution in polynomial time of certain benchmarks involving combinational multipliers. A central part of the INSTEP algorthim is simplification. Most simplifications that take place in previous tautology checkers consist of the replacement of a formula by a shorter formula that is logically equivalent. Most simplifications in INSTEP replace a formula by another formula which isnot logically equivalent, but such that satisfiability is nevertheless preserved. These new simplifications depend on the pattern of occurrence of one or more variables and particularly on theirpolarity. The simplifications used by INSTEP rest on several new theorems in an area of propositional calculus (or Boolean algebra) which is crucial to the general theory of effective simplification of propositional formulas. The primary purpose of the present paper is to demonstrate these theorems and explain the simplifications that depend on them. For the present paper we have tried INSTEP on the well-known pigeonhole problem. So far as we know INSTEP is the first implemented program to produce proofs of polynomial length for pigeonhole problems. It also produces these proofs in polynomial time.

With the rapid growth in the size and complexity of digital circuits, the possibility of bug occurrence has significantly increased. In order to avoid the enormous financial loss due to the production of buggy circuits, using scalable formal verification methods is essential. The scalability of a verification method for a specific design is proven by showing that the method has polynomial space and time complexities. Unfortunately, not all verification methods have a polynomial complexity, particularly when it comes to the verification of large and complex designs. In this paper, we propose a divide-and-conquer strategy for Polynomial Formal Verification (PFV) of complex circuits. Instead of using a monolithic proof engine to verify the entire design, we break the verification task down into several problems, which can be solved in polynomial space and time using a hybrid proof engine. As a case study, we investigate the PFV of the ALU in a RISC-V processor using our divide-and-conquer strategy.

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Many applications produce acceptable results when their underlying computations are executed in an approximate manner. For such applications, approximate circuits enable hardware implementations that exhibit improved efficiency for a given quality. Previous efforts have largely focused on the design of approximate combinational logic blocks such as adders and multipliers. In practice, however, designers are concerned with the quality of outputs generated by a sequential circuit after several cycles of computation, rather than an embedded combinational block. We propose ASLAN (Automatic methodology for Sequential Logic ApproximatioN), the first effort towards the synthesis of approximate sequential circuits. Given a sequential circuit and an output quality constraint, ASLAN creates an approximate version of the circuit that consumes lower energy, while meeting the specified quality bound. The key challenges in approximating sequential circuits are (i) to model how errors due to approximations are generated, re-circulate through the combinational logic over multiple cycles of operation, and eventually impact quality of the final output, and (ii) to select the most beneficial approximations, i.e., those that result in higher energy savings for smaller impact on quality. ASLAN addresses the first challenge by constructing a virtual Sequential Quality Constraint Circuit (SQCC) and utilizing formal verification techniques to ensure that the selected approximations meet the quality constraint. To address the second challenge, ASLAN identifies combinational blocks in the sequential circuit that are amenable to approximation, generates local quality-energy trade-off curves for them, and uses a gradient-descent approach to iteratively approximate the entire sequential circuit. We used ASLAN to automatically synthesize approximate versions of ten sequential benchmarks, resulting in energy reductions of 1.20X-2.44X for tight quality constraints, and 1.32X-4.42X for moderate quality constraints. We present case studies of using the approximate circuits generated by ASLAN in two popular applications - MPEG Encoding and K-Means Clustering - obtaining 1.32X energy savings with 0.5% PSNR degradation, and 1.26X energy savings with 0.8% increase in mean cluster radius, respectively.

In recent years, the size and complexity of digital circuits have grown drastically. Consequently, bugs may appear in a circuit in different phases of design and synthesis. If they remain undetected, they propagate to the physical chip and cause huge financial loss for the designers and manufacturers. Formal verification is an important task after design to ensure the correctness of a circuit. Recently, polynomial formal verification has gained special attention. If we prove that the space and time complexity of a verification method is polynomial, we can ensure that it is always scalable. Many digital circuits which are used in different applications have a tree-like structure. It has been proven that if a tree-like circuit is made of basic logic gates (AND, OR, NOT, NAND, and NOR), it can be verified polynomially using BDDs. However, these proofs cannot be extended to the general tree-like circuits containing XOR gates. In this paper, we propose a method to prove the correctness of a general tree-like circuit in polynomial time.

Summary form only given. Modern circuits contain up to several hundred million transistors and this number grows exponentially over time. Thus, the state-of-the-art design flows have to be improved continuously. In the meantime ensuring correctness becomes a major bottleneck. Up to 80% of the overall design costs are due to verification and even more problems are foreseeable - shrinking feature sizes lead to large process variations, increased susceptibility to radiation, etc. As a result even a correct design may contain faulty components. Thus, robustness is required, i.e. correct operation in presence of faults. Formal verification techniques have gained large attention, since they allow proving the correctness of a circuit and thereby ensure 100% functional correctness. Moreover, the underlying techniques can also be used to prove robustness of a design. Besides being more reliable, formal verification approaches have also shown to be more cost effective in many cases, since test bench creation - usually a very time consuming and error prone task - becomes superfluous. Therefore these techniques allow unveiling faulty behaviour automatically. Proving robustness in the sense of fault tolerance is important. As in any implementation step, faults may tamper the behaviour. In particular, fault tolerance may hide flaws during the standard verification step. Therefore instead of relying on the design's architectural precautions against faults, the implementation has to be proven to be fault tolerant. In this tutorial, after a brief motivation of the overall topic and definition of the problem domain, the alternative verification approaches are explained. Next, the application of the underlying formal techniques for robustness checking is considered. The standard approaches for verification are simulation, emulation and formal methods. Details are discussed related to formal verification, symbolic simulation and assertion based verification. The verification scenarios for equivalence checking (EC) and property checking (PC) are presented and the underlying proof techniques are explained. Robustness checking then also builds on the underlying formal methods. This allows analyzing the robustness of a design fully automatically. Practical scenarios covered by this model for robustness of a circuit are discussed. The model not only yields a measure for the robustness of a circuit but also shows critical parts of the implementation that should be reengineered. In comparison alternative approaches, e.g. using statistical measures, are outlined. Further references are given for all topics are given (see below). Directions for future work and research challenges are discussed.

Algorithm selection and hyperparameter tuning are critical steps in both academic and applied machine learning (ML). These steps are becoming increasingly delicate due to the extensive rise in the number, diversity, and distributed nature of ML resources. Multi-agent systems, when applied to the design of ML platforms, bring about several distinctive characteristics, such as scalability, flexibility, and robustness, just to name a few. This article proposes a fully automatic and collaborative agent-based mechanism for selecting distributed ML algorithms and simultaneously tuning their hyperparameters. Our method builds upon an existing agent-based hierarchical ML platform and augments its query structure to support the aforementioned functionalities without being limited to specific learning, selection, and tuning mechanisms. We have conducted theoretical assessments, formal verification, and analytical study to demonstrate the correctness, resource utilization, and computational efficiency of our technique. According to the results, our solution is algorithmically correct and exhibits linear time and space complexity in relation to the size of available resources. To further verify its correctness and demonstrate its effectiveness and flexibility across a range of algorithmic options and datasets, the article also presents a series of empirical results on a system composed of 24 algorithms and 9 datasets. The findings not only highlight the efficiency and scalability of the proposed approach, but also show its flexibility and openness to responding to the dynamic and distributed ML ecosystem.

Lattice-based cryptography has recently emerged as a prime candidate for efficient and secure post-quantum cryptography. The two main hard problems underlying its security are the shortest vector problem (SVP) and the closest vector problem (CVP). Various algorithms have been studied for solving these problems, and for SVP, lattice sieving currently dominates in terms of the asymptotic time complexity: one can heuristically solve SVP in time $2^{0.292d}$ in high dimensions $d$ [BDGL'16]. Although several SVP algorithms can also be used to solve CVP, it is not clear whether this also holds for heuristic lattice sieving methods. The best time complexity for CVP is currently $2^{0.377d}$ [BGJ'14]. In this paper we revisit sieving algorithms for solving SVP, and study how these algorithms can be modified to solve CVP and its variants as well. Our first method is aimed at solving one problem instance and minimizes the overall time complexity for a single CVP instance with a time complexity of $2^{0.292d}$. Our second method minimizes the amortized time complexity for several instances on the same lattice, at the cost of a larger preprocessing cost. We can solve the closest vector problem with preprocessing (CVPP) with $2^{0.636d}$ space and preprocessing, in $2^{0.136d}$ time, while the query complexity can even be reduced to $2^{\epsilon d}$ at the cost of preprocessing time and memory complexities of $(1/\epsilon)^{O(d)}$. For easier variants of CVP, such as approximate CVP and bounded distance decoding (BDD), we further show how the preprocessing method achieves even better complexities. For instance, we can solve approximate CVPP with large approximation factors $k$ with polynomial-sized advice in polynomial time if $k = \Omega(\sqrt{d/\log d})$, heuristically closing the gap between the decision-CVPP result of [AR'04] and the search-CVPP result of [DRS'14].

The high cost of correcting errors in digital design and communication protocols of e-economy systems calls for creative formal verification methods. Unlike testing and simulation, formal verification methods cover the entire system state space and all possible combination of inputs. There are two common approaches to the problem of formal verification: theorem proving and model checking. Since the deductive approach in theorem proving has many noted shortcomings the focus of the paper is on the model checking techniques. The paper explores the constraints of the application of the verification process, finds the most difficult steps in terms of space and time complexity and proposes the necessary operations to strengthen the methodology and expand it to real-world sized examples. The state explosion problem is tackled by applying binary decision diagrams (BDD) diagrams that can efficiently represent relations (functions) and sets. Finally, the paper suggests some general research directions that are likely to lead to technological advances.

Two query problems for visibility are considered. The first one is to find the visibility set of two query objects A and B of the same type as the objects of the given scene. The visibility set is characterized by those line segments connecting points on A and B which do not intersect scene objects between A and B. We show that scenes consisting of disjoint line segments in the plane can be processed into a data structure of about linear size so that the visibility set can be found in sublinear time per component of the representation chosen for the visibility set. The construction can also be applied to scenes of disjoint triangles in space. The disadvantage of possibly many components can be diminished by pre-clipping against the viewing hull of A and B. The query version of the clipping problem can also be solved in about linear space and sublinear query time. The result of the first problem is used for an efficient solution of the second problem which is to calculate the visibility sets between query object A and all scene objects visible from A.

Power estimation for CMOS sequential circuits is difficult because of sequential feedback loops embedded in the circuits. This paper presents a new method which applies probabilistic propagation and an iteration method to obtain the transition probability of circuit internal nodes. The time and space complexity of computation is improved by compacting the circuit before calculation. Experimental results show that our method is applicable even for large sequential circuits.

A register is basically known as a storage device for units in circuits. In data processing systems, they are used to immediately transfer data by using CPU. In digital electronics, shift registers are known as the sequential logic circuits that are used to store data temporally and transfer the data to its output for each and every clock pulse. Shift registers are found as digital memory unit storage in such devices as calculators, computers, etc. Based on shifting data, shift registers are classified in two types: universal shift register and bidirectional shift register. This chapter dealt with design and implementation of 8-bit universal shift register with CG scheme for minimizing power. Circuit operation is performed by Xilinx-14.7 software tool and simulated with I-SIM simulator tool using VHDL language. XPE tool is used to optimize power in the circuit. Results improved the power consumption in circuit by 40.65%. Also 4.76% of area was increased due to adding external circuitry and delay was reduced by 12.93% in the proposed design.

The integration of complex software systems such as clinical decision aid platforms and electronic health records (EHR) has substantially improved human healthcare support by enhancing diagnostic accuracy and optimizing medical workflows. Developing these systems requires meticulous processes including requirement specification, design, implementation, testing, and deployment. While numerous approaches exist for system development, formal verification through modeling has become crucial for ensuring system reliability and security. In this research, an approach based on Hierarchical Colored Petri-Nets (HCP-Nets) for process modeling and formal verification to develop an EHR system is proposed that is accurate, complete, and consistent. The World Health Organization (WHO) emphasizes integrating modern computing techniques such as data mining and machine learning into health systems in the context of viral disease outbreaks and the need for robust public health surveillance. There is a critical need for process mining and formal verification-based systems to improve data sharing and system integration in regions like Pakistan, where healthcare infrastructure and interoperability are limited. This research addresses key gaps in EHR systems including platform effectiveness, data storage consistency, data accuracy, completeness, and security against unauthorized access. The findings suggest that formal verification using HCP-Nets with model checking and process mining can greatly enhance the reliability and security of EHR systems with an accuracy of 80 5%, providing a strong foundation to advance health informatics and supporting better health outcomes in complex and diverse environments.

Self-organisation is increasingly being regarded as an effective approach to tackle modern systems complexity. The self-organisation approach allows the development of systems exhibiting complex dynamics and adapting to environmental perturbations without requiring a complete knowledge of the future surrounding conditions. However, the development of self-organising systems (SOS) is driven by different principles with respect to traditional software engineering. For instance, engineers typically design systems combining smaller elements where the composition rules depend on the reference paradigm, but typically produce predictable results. Conversely, SOS display non-linear dynamics, which can hardly be captured by deterministic models, and, although robust with respect to external perturbations, are quite sensitive to changes on inner working parameters. In this thesis, we describe methodological aspects concerning the early-design stage of SOS built relying on the Multiagent paradigm: in particular, we refer to the A&A metamodel, where MAS are composed by agents and artefacts, i.e. environmental resources. Then, we describe an architectural pattern that has been extracted from a recurrent solution in designing self-organising systems: this pattern is based on a MAS environment formed by artefacts, modelling non-proactive resources, and environmental agents acting on artefacts so as to enable self-organising mechanisms. In this context, we propose a scientific approach for the early design stage of the engineering of self-organising systems: the process is an iterative one and each cycle is articulated in four stages, modelling, simulation, formal verification, and tuning. During the modelling phase we mainly rely on the existence of a self-organising strategy observed in Nature and, hopefully encoded as a design pattern. Simulations of an abstract system model are used to drive design choices until the required quality properties are obtained, thus providing guarantees that the subsequent design steps would lead to a correct implementation. However, system analysis exclusively based on simulation results does not provide sound guarantees for the engineering of complex systems: to this purpose, we envision the application of formal verification techniques, specifically model checking, in order to exactly characterise the system behaviours. During the tuning stage parameters are tweaked in order to meet the target global dynamics and feasibility constraints. In order to evaluate the methodology, we analysed several systems: in this thesis, we only describe three of them, i.e. the most representative ones for each of the three years of PhD course. We analyse each case study using the presented method, and describe the exploited formal tools and techniques.

Deep brain stimulation (DBS) is a widely accepted treatment for the Parkinson's disease (PD). Traditionally, it is done in an open-loop manner, where stimulation is always ON, irrespective of the patient needs. As a consequence, patients can feel some side effects due to the continuous high-frequency stimulation. Closed-loop DBS can address this problem as it allows adjusting stimulation according to the patient need. The selection of open- or closed-loop DBS and an optimal algorithm for closed-loop DBS are some of the main challenges in DBS controller design, and typically the decision is made through sampling based simulations. In this letter, we used model checking, a formal verification technique used to exhaustively explore the complete state space of a system, for analyzing DBS controllers. We analyze the timed automata of the open-loop and closed-loop DBS controllers in response to the basal ganglia (BG) model. Furthermore, we present a formal verification approach for the closed-loop DBS controllers using timed computation tree logic (TCTL) properties, that is, safety, liveness (the property that under certain conditions, some event will eventually occur), and deadlock freeness. We show that the closed-loop DBS significantly outperforms existing open-loop DBS controllers in terms of energy efficiency. Moreover, we formally analyze the closed-loop DBS for energy efficiency and time behavior with two algorithms, the constant update algorithm and the error prediction update algorithm. Our results demonstrate that the closed-loop DBS running the error prediction update algorithm is efficient in terms of time and energy as compared to the constant update algorithm.