A new class of security oriented error correcting robust codes

In this paper, we study basic properties of linear network error correction codes, their construction and error correction capability for various kinds of errors. Our discussion is restricted to the single-source multicast case. We define the minimum distance of a network error correction code. This plays the same role as it does in classical coding theory. We construct codes that can correct errors up to the full error correction capability specified by Singleton bound for network error correction codes recently established by Cai and Yeung. We propose a decoding principle for network error correction codes, based on which we introduce two decoding algorithms and analyze their performance. We formulate the global kernel error correction problem and characterize the error correction capability of codes for this kind of error.

Error correction coding, channel coding, also known as error control coding, is to add some redundant code elements, or check code elements, to form a correlated sequence of code elements—code words and to use the correlation property between code elements to detect and correct errors when decoding. Different error correction coding schemes have different error detection and correction capabilities. This paper designs a combination of parity check and cyclic redundancy check (CRC) to improve the error detection and correction capabilities with minimum cost, so that the system can transmit information more efficiently while also having high transmission reliability.

Modified Packet Combining (MPC) scheme is an error correction scheme, which can correct double or, higher bit errors. In some earlier work, a scheme known as Packet Reversed Packet Combining (PRPC) scheme that will correct error if occurs at same bit location of erroneous copies, was studied. Both PRPC and MPC scheme are believed to offer higher throughput and better error correction capability at high bit error rate (BER) and large packet size only. Exact analysis was performed to substantiate this claim of higher throughput and better error correction capability in high as well as in low bit error rate (BER) for large and medium packet size. To combat high bit error rate some researches proposed to use Error Correction Code (ECC) in place of Error Detection Code (EDC) in ARQ scheme. But no conclusive result is found to justify the idea in terms of throughput. The current investigation is an attempt to explore the basic gap. In this paper, we investigate the exact analysis of both PRPC and MPC in a Modified way over Conventional PRPC, and report the findings thereof. We propose a combined protocol of Modified PRPC and MPC, and find that it will offer higher throughput and better error correction capability at high and low BER with medium and large packet size as we have used MPC (Modified Packet Combining) scheme with PRPC (Packet Reverse Packet Combining) scheme in a Modified way by combining BEC (Backward Error Correction) with FEC (Forward Error Correction) Codes for Mobile Communication and Networks.

Error detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.

An [$$n, k, d$$n,k,d] code is a binary linear code of block length $$n$$n, dimension $$k$$k and minimum Hamming distance $$d$$d. Since the minimum distance determines the error detection or correction capability, it is desired that $$d$$d is as large as possible for the given block length $$n$$n and dimension $$k$$k. One of the most fundamental problems in coding theory is to construct codes with best possible minimum distances. This problem is very difficult in both theory and practice. During the last decades, it has proved that the class of quasi-cyclic (QC) codes contain many such codes. In this paper, augmentation of binary QC codes is studied. A new augmentation algorithm is presented, and 10 new $$h$$h-generator QC codes that are better than previously known code have been constructed. Furthermore, Construction X has been applied to obtain another 18 new improved binary linear codes. With the standard construction techniques, a total of 124 new binary linear codes that improve the lower bound on the minimum distance have been obtained.

The increasing demand for high-density and high-speed digital optical recording systems has made the development of advanced coding and signal processing techniques for fast and reliable data recovery increasingly important. In recent years, the parity-check (PC)-code-based reception technique has been widely studied for magnetic recording systems, and it is projected to be highly promising for high-density optical recording. The PC code is an inner error correction code (ECC), which can detect dominant short error events of the system, using only a few parity bits. This reduces the loss in error correction capability of the outer ECC due to random short errors and results in a simple and efficient solution to improve the overall performance. This thesis is dedicated to the design and analysis of PCcode- based recording systems to achieve higher recording capacity with low implementation complexity, for high-density blue laser disc systems. In particular, most of the key components of the PC-code-based optical recording system have been designed and optimized for different recording densities, and different proportions of white noise and media noise. During the development of advanced coding and detection techniques, it becomes necessary to investigate the system’s performance with different coding schemes and recording densities. In Chapter 2 of the thesis, we propose a generalized Braat-Hopkins model for optical recording channels, which provides a fair basis for the performance comparison of detection schemes over different coding schemes and recording densities, for channels with additive, white Gaussian noise (AWGN) and media noise. Various basic issues associated with the PC-code-based systems are investigated in Chapter 3. These include bounds for bit error rates and error event probabilities, the dominant error events at channel detector output, different PC codes, simple and efficient post-processors, the impact of error events that are split across data block boundaries and the corresponding remedy, as well as the effects of code rates and recording densities. Simulation results show that a 4-bit PC code achieves the best performance. The corresponding bit error rates (BERs) are very close to the performance bounds, at both nominal and high densities. Constrained codes, which serve as a key component in the read-write channel of data storage systems, are desired to have a high code rate with low-complexity encoder/decoder. In Chapter 4, we investigate the design of certain capacity-approaching constrained codes for optical recording systems. In particular, we derive analytically the relationship between the number of encoder states and the maximum size of these codes. We identify the minimum number of encoder states that maximizes the code rate, for any desired codeword length. The design of constrained PC codes is key to the development of PCcode- based systems, and the systematic design of efficient constrained PC codes remains a challenging problem. In Chapter 5, we propose a general and systematic code design technique for constructing capacity-approaching constrained PC codes, which can detect any type of error events of the system, with the minimum code rate loss. Compared to the rate 2/3 code without parity, the newly designed constrained 4-bit PC code achieves a performance gain of 2 dB at nominal density, and 1.5 dB at high density, at BER = 10-5. As the dominant noise for high-density optical recording systems, media noise severely degrades the performance of channel detectors and postprocessors that are designed for AWGN. In Chapter 6, we propose two novel modifications to the bit detector to combat media noise. We further develop a data-dependent post-processing scheme for error correction. Compared to the system designed without considering media noise and without PC codes, the overall performance gain of the developed scheme can be more than 11 dB at high media noise levels. In data storage systems, the ECC failure rate (EFR) serves as the ultimate measure of the data recovery performance. In Chapter 7, we develop semi-analytical approaches for estimating the EFR, and analyze EFRs for the developed PC-code-based systems, for the cases without and with interleaving. Our analysis shows that with the optimum interleaving degrees, compared to the rate 9/13 code without parity, the 2-bit PC code achieves a gain of around 0.5 dB, and the 4-bit PC code gains 0.6 dB, at high record ing density and EFR = 10-16. The thesis concludes in Chapter 8 with some suggestions for further work.

A novel steganographic QR code algorithm, which not only coveys the secret into the widely-used QR barcode but also preserves the readability of QR content and the capability of error correction, is presented in this article. Different from the conventional applications for QR barcode, the designed algorithm conceals the secret into the QR modules directly by exploiting the error correction capability. General browsers can read the QR content from the QR code via barcode readers; however, only the authorized receiver can further reveal the secret from the QR code directly. The new mechanism can convey a larger secret payload along with adjustment of the QR version and error correction level. Moreover, the blind property allows the receiver to reveal the secret without the knowledge of the embedded position of modules. Experimental results demonstrate that the new algorithm is secure, efficient and feasible for the low-power QR readers and mobile devices.

This thesis summarizes research on the design and implementation of the unequal error protection (UEP) mechanism for the RaptorQ forward error correction (FEC) scheme. As part of this research, existing UEP mechanisms for various fountain codes were evaluated. Two new UEP methods were proposed for the RaptorQ coding scheme, and these methods were designed with the assumption that all of the symbols in a source block have the same priority. The first method, known as priority based overhead number (PBON), was based on the priority encoding transmission model, wherein the error-correction capability was altered by making the number of overhead symbols proportional to the priority of the information symbols. This method was extended to the RaptorQ codes with some changes and evaluated for failure probability and performance. The second method, known as priority based precode ratio (PBPR), was designed by changing the precode properties of the RaptorQ codes. The ratio of precode symbols to Luby-Transform symbols in the RaptorQ codes was changed to achieve different error correction capabilities for each priority group. The scheme with the higher number of precode symbols provided superior error-correction capabilities compared to those with fewer precode symbols. Both methods were empirically verified through simulation in the C++ programming language. The results demonstrated that the higher-importance class depicted a better error-correction capability than the lower-importance class.

The quest for an efficient computational approach to neural connectivity problems has undergone a significant evolution in the last few years. The current best systems are far from equaling human performance, especially when a program of instructions is executed sequentially as in a von Neuman computer. On the other hand, neural net models are potential candidates for parallel processing since they explore many competing hypotheses simultaneously using massively parallel nets composed of many computational elements connected by links with variable weights. Thus, the application of modeling of a neural network must be complemented by deep insight into how to embed algorithms for an error correcting paradigm in order to gain the advantage of parallel computation. In this dissertation, we construct a neural network for single error detection and correction in linear codes. Then we present an error-detecting paradigm in the framework of neural networks. We consider the problem of error detection of systematic unidirectional codes which is assumed to have double or triple errors. The generalization of network construction for the error-detecting codes is discussed with a heuristic algorithm. We also describe models of the code construction, detection and correction of t-EC/d-ED/AUED (t-Error Correcting/d-Error Detecting/All Unidirectional Error Detecting) codes which are more general codes in the error correcting paradigm.

Window-constrained interconnect-efficient progressive edge growth LDPC codes

This paper investigates the effects of noise‐induced transmission errors on the performance of compression coding methods for still pictures. The following four coding methods are considered: (1) adaptive cosine transform coding; (2) DPCM coding; (3) adaptive block coding; and (4) vector quantization coding. First, the relations among the bit error rate, signal‐to‐noise ratio (SNR), and code lengths by these coding methods are compared in the case of transmission without error control. Adaptive cosine transform coding and adaptive block coding require control information for adaptivity; therefore, they are investigated with and without transmission errors in the coding control information. Further, transmission with error control is studied for sending control information. Considering the error control methods, both automatic repeat request and forward error correction are considered. In these cases SNR deterioration by transmission noise beyond error correction capability and the amount of additional data required for error detection/correction or retransmission are examined. BCH codes are used for error detection and correction.

Scratchpad memories (SPM) are often used to boost the performance of application-specific embedded systems. In embedded systems, main memories are vulnerable to external attacks such as bus snooping or memory extraction. Therefore it is desirable to guarantee the security of data in a main memory. In software-managed SPM, it is possible to provide security in main memory by performing software-assistant encryption. In this paper, we present an efficient compiler for security aware scratch pad Memory (SA-SPM), which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e. stack, heap, code, and static variables) in a SPM-based system. Furthermore, to reduce the energy consumption and improve the lifetime of a non-volatile main memory by decreasing the number of bit flips, we propose a new dual encryption scheme for a SPM-based system. Our experimental results show that the proposed dual encryption scheme reduces the number of bit flips by 31.8% compared with the whole encryption.

Networks-on-Chip (NoC) is quickly becoming the standard communication paradigm for the growing number of cores on the chip. The error correction code (ECC) is widely adopted in error correction NoCs to ensure that the data is correct. As the probability of multiple errors gradually increases, the trade-off between fault-tolerance and overhead requires careful consideration by designers. Therefore, this paper aims to improve the cost-effectiveness rather than just error correction capability. We propose HCER, a high cost-effectiveness multi-bit fault-tolerant NoC router. We first propose a speculative router architecture, which reduces the performance loss introduced by ECC. Secondly, we use 2D code instead of the traditional BCH code for multi-bit error-tolerant design, enhancing the error correction capability. As a result, our design could achieve a 16x improvement in cost-effectiveness over the baseline design under synthetic patterns and the PARSEC benchmark when under the same error correction capability. In addition, our router does not introduce large hardware overheads.

The various codes are used for the error detection and correction in the field of communication. Some are for the single bit error and some are for the multiple bits error. Reed-Muller algorithm realizes the ability of multiple bits error detection and correction. With the superior error correction capability, these codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. Reed-Muller codes cover a wide range of service requirements and diverse interference conditions in wireless applications and can operate at both high and low code rates. In this paper, the comparison of Reed-Muller codes with different other codes for error detection and correction of multiple bits is proposed and further we can implement it on a Xilinx field programmable gate array (FPGA) device. Using Reed-Muller method the data is transferred from transmitter to receiver without any error. The error detection and correction principle and realization methods are described in detail. The multiple bits error detection and correction with Reed-Muller algorithm method can improve the bit error rate and packet error rate effectively.

Error control (detection and correction) of data plays a pivotal role in networking to facilitate the reliable transmission of messages from source to destination. Convolution code is one of the popularly known error control mechanism which is considered superior to several legacy error control algorithms like the Hamming code. The Fano algorithm is a sequential decoding algorithm used to decode long constraint length convolution codes. However, this algorithm has failed to offer 100% error detection and correction capabilities. These lead to the inferior performance of this algorithm to correct errors at the destination. This paper proposes an enhanced Fano (e-Fano) algorithm that offers 100% error detection and correction up to finite bits of error. Through the MATLAB simulations, e-Fano and the conventional Fano algorithm are compared for the % of error detection and correction in the received data.