A new hierarchical approach to test-pattern generation

The improvement in Integrated Circuits density increases the fault occurrence probability. To ensure proper operation of critical systems, circuits testing becomes a task of extreme importance. Over the years, several methods have been proposed to optimize ATPGs (Automatic Test Pattern Generation). The optimization in test pattern generation aims to reduce the set of test vectors to be applied to circuits. Several techniques explore the concept of equivalent faults (Fault Collapsing). BDDs (Binary Decision Diagram) are one of the data structures explored to solve the problem. With a low capacity to handle large circuits, many extensions and modifications in BDDs have been proposed in the literature. This work aims to review Fault Collapsing concepts and investigate the efficiency of the BDDs proposed in the literature. A case study is done to compare classic techniques with BDDs extensions.

Reduction of OBDDs in linear time

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram (BDD). First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

Digital circuit’s complexity and density are increasing while, at the same time, more quality and reliability are required. These trends, together with high test costs, make the validation of VLSI circuits more and more difficult. In this project we introduce the automatic test pattern generator with multiple single input change (SIC) vectors for post silicon validation schemes. Choosing a best device leads to challenges in various factors, In this paper performs a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The designed TPG is flexible to both the test-per-clock and the test-per-scan schemes.A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results show that the produced MSIC sequences have the favorable features of uniform distribution and low input transition density. The performances of the designed TPGs and the circuits under test with 45 nm are evaluated. Simulation results with ISCAS benchmarks demonstrate that MSIC can save test power and impose no more than 7.5% overhead for a scan design. It also achieves the target fault coverage without increasing the test length.

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35 /spl mu/m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

The scaling of circuit design technology to ultra deep submicron has increased the sensitivity of circuit technology to various noise mechanisms such as power supply noise and leakage current noise, etc. The propagation of noise can happen through various modes like the power supply and the substrate to a sensitive receptor. The power supply noise can reduce the actual voltage level reaching a device, results in the loss of signal integrity. The type of noise may also cause the degradation of switching speed, timing faults, or logic functional failures. In this paper, a new approach is presented for the test generation of power supply noise in digital circuits, the approach is based on the binary decision diagrams. The test vectors of power supply noise are generated by building and operating several binary decision diagrams, such as the binary decision diagrams respectively corresponding to the normal circuits and the circuits whose signal lines have been assigned special logic values. A lot of experimental results show that if there are test vectors for the power supply noise in a circuit, then the test vectors can be generated by the approach proposed in this paper.

The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

(Ordered) binary decision diagrams are a powerful representation for Boolean functions and are widely used in logical synthesis, verification, test pattern generation or as part of CAD tools. NC-algorithms are presented for the most important operations on this representation, e.g. evaluation for a given input, minimization, satisfiability, redundancy test, replacement of variables by constants or functions, equivalence test and synthesis. The algorithms have logarithmic run time on CRCW COMMON PRAMs with a polynomial number of processors.

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size.

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG

Our new technique for estimating transition probabilities of internal signals in combinational circuits uses Markov chains and reconvergence regions. To efficiently implement the computation, we use ROBDDs (reduced, ordered binary decision diagrams). Accounting for temporal dependence of signals, multiple concurrent transitions, and mutual dependence of internal signals, the technique provides an exact computation for small circuits and an approximate estimate for large circuits. Experimental results show the estimation technique is fast with only small inaccuracies.

Lately, research has been focused on the problem of extracting the main unsatisfiable cores from infeasible constraints. The main reasons of infeasibility can be represented by subsets of unsatisfied clauses referred to “Minimal Correction Subsets”. Various developed algorithms for computing MCSes can be used for fault detection technique which is considered a core of SAT-based Automatic Test Pattern Generation (ATPG) on digital VLSI circuits. This paper presents an efficient CPU-GPU algorithm for extracting the complete MCSes that can be optimized on NVIDIA General Purpose Graphics Processing Unit paradigm which is considered one of the most common platforms for GPU parallel computing. Our proposed algorithm is evaluated using a C++ algorithm for generating and reducing a SAT instance of VLSI digital circuits from ISCAS'85, ISCAS'89 and synthetic benchmarks. The proposed algorithm, utilizing our presented parallel SAT-solver, delivers about 1.4x speedup compared to the CUDA@SAT tool.

Symbolic verification based on Binary Decision Diagrams (BDDs) has proven to be a powerful technique for ensuring the correctness of digital hardware. In contrast, BDDs have not caught on as widely for software verification, partly because the data types used in software are more complicated than those used in hardware. In this work, we propose an extension of BDDs for dealing with dynamic data structures. Specifically, we focus on queues, since they are commonly used in modeling communication protocols. We introduce Queue BDDs (QBDDs) which include all the power of BDDs while also providing an efficient representation of queue contents. Experimental results show that QBDDs are well-suited for the verification of communication protocols.

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to "design-in" quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits.