A new input matching technique for ultra wideband LNAs

In this paper, a Ku-band LNA at 13– 16 GHz is designed with low NF, high gain, and low power consumption for space application This paper presents high gain, too low noise figure, and low power consumption low noise amplifier (LNA). Simultaneously achieving high gain and low noise figure (NF), a popular source degeneration technique is used. Also for achieving high gain, this work is implemented with three-stage cascade source degeneration technique. The proposed work also aims to optimize the input, output and isolation losses. For achieving a low noise figure, InGaAs HEMT technology is used and Ku Band at 13–16 GHz LNA is designed for space application. Simulated results are NF of 1.008 and 0.719 dB and gain of 29.70 and 22.83 dB. The less than −12 dB is achieved for return losses of input and output. The Stability Factor and Mu1 are greater than 3 at desired 13–16 GHz. The amplifier biasing V ds , I ds is 2V and 10 mA respectively are chosen. The Keysight Technology Advanced Design System is used for simulating all parameters. The LNA consumes the power of 250 mW from the simulated values.

In this paper, a narrow-band low-noise amplifier (LNA) is described in 180nm digital CMOS technology. By means of an inductive degenerated common source amplifier with a gate inductor gives an excellent input matching. The output matching is obtained by using the output stage including output buffer. In the proposed LNA, the cascode technique is adopted in order to improve the noise figure and isolation. The LNA provides high gain and low noise figure and good reverse isolation over the frequency range as well as good stability. The LNA is simulated with a TSMC 0.18-J.lm CMOS technology. The input and output reflection coefficients are −16.45 dB and −16.92 dB at an operation frequency of 10 GHz, respectively. The noise figure of the LNA remained under 2.95 dB from 9.75 GHz to 10.25 GHz with minimum value of 2.8 dB. Additionally, a high gain with average value of 14.44 dB and a maximum value of 15.69 dB is achieved for the whole bandwidth of 500 MHz. The power consumption at 1.8-V supply voltage without an output buffer is only 8.44 mW.

GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6–3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.

The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words. In low noise amplifier (LNA) design, a prominent trade-off usually exist between noise-figure (NF) and gain. In this paper, impact of quality-factor (Q) of the inductors used in LNA design on the overall noise-figure and gain parameters are discussed. To understand the efficacy of the dependency of Q of inductors on NF, LNA with inductor available in UMC 0.18 μm Process Design Kit and LNA with parameterized-cell (pcell) based layout optimized high Q tapered inductors are realized, simulated and compared. Simulations study are carried out on a cascode source degenerated LNA. First, the LNA design is studied for different values of finite Q using library inductors. It is observed that the noise figure is reduced by about 65% (2.66 dB–1.61 dB) and gain is improved by about 30.2% (7.63–9.94) for the same design when Q of the inductors are increased from 10 to 30. Finally, the design is implemented using layout optimized high Q tapered inductors achieving lower noise figure of 1.2 dB with a better gain value of 16.45 and input return loss of −29.31 dB.

This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.

PVT-compensated low voltage LNA based on variable current source for low power applications

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

This paper presents the realization of high gain low Noise Figure (NF) Low Noise Amplifier (LNA) employing the variable gain amplifier. The high gain is achieved by cascading three stages while the low NF is achieved by employing the resistive feedback in the input stage. The linearity is achieved by employing the source degeneration technique. The variable gain amplifier gets turned on/off by the input signal causing the change in the transconductance of the LNA and hence the gain of LNA varies according to the input signal strength. The results show that maximum gain for the realized LNA is 21.34 dB at 1.72 GHz for M7 ON position while during M7 OFF position, the maximum gain achieved is 26.05 dB at 1.72 GHz frequency. The S11 value is less than –9 dB for the frequency range of 1.65 GHz to 3.9 GHz, i. e., having the bandwidth of 2.25 GHz and it is matched for the 50 Ω termination at input and output port. The minimum value of the NF during low conductance is 2.88 dB while during the high conductance it is 2.82 dB.

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only 3.2 mA from a 3.3 V supply, resulting in a total power consumption of 10.56 mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain (S21) of 15.2 dB at 868 MHz, with an input reflection coefficient (S11) of −6.9 dB and an output reflection coefficient (S22) of −6.3 dB. The amplifier achieves a minimum noise figure of approximately 1.77 dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks.

Heuristic receiver for implantable UWB applications

Recent advancements in semiconductor technologies supports high data rate communications in V-band. Particularly 60 GHz encourages short range multi Gbps transmission suitable for multimedia applications. The first block of the receiver, Low Noise Amplifier (LNA) should have high gain requirements simultaneously maintaining low noise Figure (NF). This work consists of designing Variable Gain (VG) LNAs over the desired bandwidth (57–64) GHz in the V – Band. Variable loads formed by active devices are used to change body transconductance of amplifying transistor. It is found that better tuning range of 19.23 dB/V is achieved with lower noise Figure of 1. 4SSdB for PMOS variable load LNA. Almost 3.57 GHz bandwidth is achieved with figure-of-the-merit (FOM) of >S in all LNAs.

In this paper, a novel active diplexer based on low-noise amplifiers (LNAs) using multi-functional composite right/left-handed input matching circuit (CRLH-IMC) is proposed. Since each CRLH-IMC has optimized impedance for targeted LNA performances as well as the required isolation characteristics, an active diplexer with gain and low noise figure (NF) can be realized by placing a single input port between two LNAs with CRLH-IMCs. The proposed active diplexer can reduce overall system dimension and loss by removing passive diplexer. In addition, diplexer performances such as insertion loss and isolations can now be controlled by an amplifier design. In this paper, the active diplexer prototype operating at 1.5 GHz and 2.6 GHz is designed and fabricated. The measured results show good agreement with the simulated results.

There is increasing interest in wireless receivers that can work with different standards at different frequencies. The usual way of implementing a low noise amplifier (LNA) block in such a receiver is to use separate narrowband LNAs. In this paper, a wideband LNA is presented, with negative feedback by means of a double loop feedback network to achieve simultaneously a low noise figure and input matched impedance for a wide range of frequencies. The designed LNA has a noise figure lower than 3 dB, input impedance matched to 50 /spl Omega/ and a gain above 12 dB for a frequency range between 700 MHz; and 5 GHz. The LNA has been designed in 0.18 /spl mu/m CMOS technology from National Semiconductor. It consumes 18.9 mW for a supply voltage of 1.8 V.

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.