Heuristic receiver for implantable UWB applications

One of the important components of a receiver is the low noise amplifier (LNA). The challenges of LNA design include ability to achieve high gain, low noise figure, and better linearity at low power consumption within the required frequency. In this article, our design is based on Impulse Response (IR) Ultra Wide‐Band (UWB) transceiver operating at 3.1–4.6 GHz. Hence, the LNA designed has been optimized for low noise figure, considerably high gain and better linearity at low power consumption, which make it suitable for implantable radio application. The process technology used here is 0.25 μm CMOS Silanna process. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1399–1401, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27588

In this paper, a Ku-band LNA at 13– 16 GHz is designed with low NF, high gain, and low power consumption for space application This paper presents high gain, too low noise figure, and low power consumption low noise amplifier (LNA). Simultaneously achieving high gain and low noise figure (NF), a popular source degeneration technique is used. Also for achieving high gain, this work is implemented with three-stage cascade source degeneration technique. The proposed work also aims to optimize the input, output and isolation losses. For achieving a low noise figure, InGaAs HEMT technology is used and Ku Band at 13–16 GHz LNA is designed for space application. Simulated results are NF of 1.008 and 0.719 dB and gain of 29.70 and 22.83 dB. The less than −12 dB is achieved for return losses of input and output. The Stability Factor and Mu1 are greater than 3 at desired 13–16 GHz. The amplifier biasing V ds , I ds is 2V and 10 mA respectively are chosen. The Keysight Technology Advanced Design System is used for simulating all parameters. The LNA consumes the power of 250 mW from the simulated values.

Inspired from continuous growth in the field of low power and low noise wireless communication devices, a low noise amplifier (LNA) using self-body biased common-gate (CG) configuration is presented in this paper. The proposed LNA is designed for 3–14[Formula: see text]GHz ultra-wideband (UWB) frequency range using 90[Formula: see text]nm CMOS process. Common-gate configuration with self-body biasing has been used at the input stage to provide wideband input matching with low noise figure (NF) for the complete UWB frequency. An impedance matching network consisting of parallel to series RLC network has been used between common-gate and cascaded common source (CS) stages. Two stages of the CS configuration have been used for bandwidth enhancement and to increase the power gain (S[Formula: see text]) with acceptable NF. Buffer stage at the output has been used to achieve output reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.8[Formula: see text]dB. The proposed LNA achieves an average S[Formula: see text] of 15.9[Formula: see text][Formula: see text][Formula: see text]0.7[Formula: see text]dB with a maximum of 16.7[Formula: see text]dB at 3.0[Formula: see text]GHz and NF of 1.68–2.7[Formula: see text]dB for 3.1–10.6[Formula: see text]GHz UWB frequency range. It provides input reflection coefficient (S[Formula: see text]) less than [Formula: see text]10.2[Formula: see text]dB, reverse isolation (S[Formula: see text]) less than [Formula: see text]75.8[Formula: see text]dB and a NF of 1.68–4.0[Formula: see text]dB throughout the proposed UWB frequency range. The proposed LNA provides input 1[Formula: see text]dB compression point (P1dB) of [Formula: see text]13[Formula: see text]dBm and input third-order intercept point (IIP3) of [Formula: see text]8[Formula: see text]dBm at 6[Formula: see text]GHz. It consumes 20.1[Formula: see text]mW of power from a 1.2[Formula: see text]V power supply.

Power efficient ultra-wideband based wireless communication for wireless body area network applications

A noise reduction input matching technique for broadband low noise amplifiers (LNAs) is presented. The proposed LNA employs a positive active feedback network besides of the conventional common-gate (CG) amplifier to achieve both wideband input signal matching and low noise figure (NF), simultaneously. Compared to the conventional broadband noise cancellation techniques, the presented approach achieves the same NF with much less power consumption and high linearity. Circuit level analysis and simulation results are provided to verify the usefulness of the proposed LNA technique. In contrast to the traditional noise cancellation circuit, the proposed LNA does not degrade the linearity and its IIP3 is similar to the simple common-gate LNA. The proposed technique is applied to an LNA operating in 2∼6.5GHz bandwidth.

This paper presents a new design of inductorless wideband front-end receiver using 130 nm CMOS technology for LTE bands of 0.7 GHz to 3 GHz. The RF front-end receiver consists of the microstrip antenna, self-bias resistive feedback low-noise amplifier, active balun and folded mixer architecture. The miniature antenna provides good matching results for the entire band of interest. Optimization of low-noise amplifier using linearization technique followed by NMOS switches mixer stage are effectively used to achieve maximum gain, low noise figure, and low power consumption. The designed receiver exhibits a maximum gain of 22 dB, maximum noise figure of 7.5 dB, minimum 3rd order intercept point (IIP3) of −9.2 dBm, and DC power consumption of 22 mW at 1.2 V power supply. Using these optimizations, our proposed receiver can be a good candidate for LTE applications.

While an LNA (low noise amplifier) has several requirements (high gain, low noise figure, low in out VSWR, and high stability), it is difficult to satisfy the desired specifications all together. Moreover, W-CDMA (wideband code division multiple access) receiving systems require high linearity to have good sensitivity, and the portable communication devices have low power consumption. It is important to select an appropriate transistor and have some trade offs among the required specifications to satisfy and optimize various specifications. We designed and fabricated an LNA which can be used in a W-CDTWA receiving system. For improving the input VSWR and stability an inductance composing of series feedback was added to the emitter, and for acquiring high-linearity at low DC bias current the by-passing method was used. The fabricated LNA had a power gain of 15.33 dB, NF 2.17 dB, S/sub 11/ 9.53 dB, S/sub 22/ 35.91 dB at 2.16 GHz, and IIP/sub 3/ +5.34 dBm with 10 MHz channel spacing. We think that this LNA can be applied to a W-CDMA receiving system.

A 20–29 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with excellent input return loss (S11), flat and high power gain (S21), and flat and low noise figure (NF) is demonstrated. Wideband input impedance matching was achieved by using the proposed T-match input network to generate two S11 dips. Flat and high S21 was achieved because the inductive-peaking second stage and the current-reused final two stages can compensate the gain degradation of the source-degenerative first stage at medium and high frequencies, respectively. Flat and low NF was achieved by adopting a slightly under-damped Q-factor for the second-order NF frequency response. The LNA consumed 22.07 mW and achieved S11 of −15.5 to −26.8 dB, S21 of 16.2±2.5 dB, minimum NF (NFmin) of 3.1 dB (at 20 GHz), and an average NF of 3.6 dB over the 20–29 GHz band of interest, one of the best reported average NF performances for a 24 GHz band CMOS LNA with bandwidth wider than 6 GHz in the literature.

GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6–3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.

A new ultra-wideband 0.18-μm CMOS sampling receiver frontend was developed. It includes a low-noise amplifier (LNA) and a sampler and achieves high gain, fast sampling, low noise figure, low power consumption, and enhanced RF-power efficiency. The LNA and sample-and-hold capacitor are switched using two synchronized strobes generated on-chip. Measured results show performance of 9 to 12 dB voltage conversion gain, 16 to 25 dB noise figure, and power consumption of only 21.6 mW (with buffer) and 11.7 mW (without buffer) across DC to 3.5 GHz with 100-MHz sampling frequency.

A novel method for Ultra Wideband (UWB) receiver design in Wireless Body Area Network (WBAN) is proposed in this study. The method is based on the Improved Memetic-Algorithm (IMA), with the output Signal-to-Noise Ratio of the receiver (SNR<em>out</em>) is optimized. By relating the target SNR<em>out</em> to the parameters of main components, including Low Noise Amplifier (LNA), mixer and base-band Low Pass Filter (LPF), an objective function was built for multi-parameters optimization in the IMA. The optimum values of small signal gain, noise factor and inter-modulation product can then be calculated. Two PSO algorithms, CLPSO (Comprehensive Learning Particle Swarm Optimizer) and AdpISPO (Self-adaptive Intelligent Single Particle Optimizer) were introduced in the IMA for different particles updating. The proposed method was validated through extensive experiments. Comparing to conventional PSO approaches, the proposed method can converge to the optimum design with less iteration.

The abstract should summarize the contents of the paper in short terms, i.e. 150–250 words. In low noise amplifier (LNA) design, a prominent trade-off usually exist between noise-figure (NF) and gain. In this paper, impact of quality-factor (Q) of the inductors used in LNA design on the overall noise-figure and gain parameters are discussed. To understand the efficacy of the dependency of Q of inductors on NF, LNA with inductor available in UMC 0.18 μm Process Design Kit and LNA with parameterized-cell (pcell) based layout optimized high Q tapered inductors are realized, simulated and compared. Simulations study are carried out on a cascode source degenerated LNA. First, the LNA design is studied for different values of finite Q using library inductors. It is observed that the noise figure is reduced by about 65% (2.66 dB–1.61 dB) and gain is improved by about 30.2% (7.63–9.94) for the same design when Q of the inductors are increased from 10 to 30. Finally, the design is implemented using layout optimized high Q tapered inductors achieving lower noise figure of 1.2 dB with a better gain value of 16.45 and input return loss of −29.31 dB.

This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.

This paper presents a 77 GHz Receiver (Rx) for automotive radar with high linearity, low noise figure (NF) and reconfigurable gain and bandwidth of the analog baseband (ABB), implemented in TSMC 65 nm CMOS general purpose (GP) technology. The Rx includes a low-noise amplifier (LNA), sharing the transconductance stage with a double-balanced mixer, an LO chain with a frequency doubler and an analog baseband. The entire Rx consumes 123 mW. Measurement results show that the input 1 dB compression point (P 1dB ) is −14 dBm at 81 GHz, a conversion gain (CG) of 20.5–62.5 dB is digitally tunable at 77 GHz, and an NF of 11.2–18.3 dB is achieved over the frequency range of 76–81 GHz.

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.