A new performance measure for characterizing fault rings in interconnection networks

In the network of Tori with faults, many fault-tolerant routing schemes have been proposed based on the fault models. Although these schemes enable the packets to bypass the fault regions without causing any deadlock in the network, they have the common shortcoming. Since all blocked packets would be misrouted on the fault ring, the fault ring would undertake heavier traffic load, which makes it be the bottleneck of the network. In this paper, targeting this drawback in the faulty network, we have proposed the concept of outer ring, which is comprised of the nodes neighboring to the fault ring and shares the shape with the fault ring. Through designing a kind of fault-tolerant routing scheme to lessen the traffic load into the fault ring, the bottleneck effect of the fault ring could be alleviated so that the performance of the network could be improved.

The static network performance and dynamic communication performance of the Hierarchical Torus Network (HTN) using dimension-order routing algorithm have already been evaluated and shown to be superior to the performance of other interconnection networks. However, the assessment of the dynamic communication performance improvement of HTN by the efficient use of both the physical link and virtual channels has not yet been evaluated. This paper addresses three adaptive routing algorithms - link-selection, channel-selection, and a combination of link-selection and channel-selection - for the efficient use of physical links and virtual channels of an HTN to enhance dynamic communication performance. It also proves that the proposed adaptive routing algorithms are deadlock-free with 3 virtual channels. The dynamic communication performances of an HTN is evaluated by using dimension-order routing and proposed adaptive routing algorithms under various traffic patterns. It is found that the dynamic communication performance of an HTN using these adaptive routing is better than when the dimension-order routing is used, in terms of network throughput.

We obtain the conditional fault diameter of the k-ary n-cube interconnection network. It has been previously shown that under the condition of forbidden faulty sets (i.e. assuming each non-faulty node has at least one non-faulty neighbor), the k-ary n-cube, whose connectivity is 2n, can tolerate up to 4n-3 faulty nodes without becoming disconnected. We extend this result by showing that the conditional fault-diameter of the k-ary n-cube is equal to the fault-free diameter plus two. This means that if there are at most 4n-3 faulty nodes in the k-ary n-cube and if every non-faulty node has at least one non-faulty neighbor, then there exists a fault-free path of length at most the diameter plus two between any two non faulty nodes. We also show how to construct these fault-free paths. With this result the k-ary n-cube joins a group of interconnection networks (including the hypercube and the star-graph) whose conditional fault diameter has been shown to be only two units over the fault-free diameter.

In this paper, we present an adaptive fault-tolerant wormhole routing algorithm for hypercubes by using 4 virtual networks. Each node is identified to be in one of the four states: safe, ordinarily unsafe, strongly unsafe, and faulty. Based on the concept of unsafe nodes, we design a routing algorithm for hypercubes that can tolerate at least n-1 faulty nodes and can route a message via a path of length no more than the Hamming distance between the source and destination plus four. Previous algorithms which achieve the same fault tolerant ability need at least 5 virtual channels per physical channel. Simulation results show that our algorithm outperforms previous known results.

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

In an often-cited paper, A. Karp [1] commented on the “sorry state” of parallel programming, lamenting the difficulties in programming and debugging parallel programs on existing programming models. Indeed, a variety of programming models have been proposed with not entirely satisfactory results. In this note, we focus on the world of massively parallel shared memory machines and examine programming models for these machines. A shared memory parallel computer is one in which the processors communicate by reading and writing data words to a shared memory. We consider shared memory parallel computers with the following characteristics. Each processor has some fast, relatively small, private memory (e.g. registers, cache). There is a large shared memory composed of a series of memory banks that are accessible by all processors via an interconnection network. Each processor has one such memory bank which is local to it, i.e. it can access the bank without going through the interconnection network. The access time to a memory bank for a processor depends in part on the lengths of the links traversed and the number of hops in the path from the processor to the bank. Special coprocessors take care of interprocessor communication: both programmers and processors are relieved of the burden of routing the parallel requests to shared memory, including handling intermediate hops of requests traveling to their destinations. In order to overcome the high latency of accessing global memory, the parallel computer supports the pipelining of global memory accesses through the network. This implies that the interconnection network has sufficient bandwidth to handle the multiple requests per processor.

The optimization of multicast communication for regular interconnection networks (IN) has been the subject of many studies in the literature. Extensions, however, the analysis of IN with arbitrary topology and background traffic poses a great challenge. In this context, a novel heuristic algorithm for multicast communication is proposed for arbitrary IN with finite capacity and bursty background traffic. The scheme facilitates interprocess communication amongst parallel computers and Grid computing networks as well as local and wide area networks and it is applicable to a single-port mode of message passing communication. The scheme utilizes a queue-by-queue decomposition algorithm for arbitrary open queueing network models, based on the principle of maximum entropy, in conjunction with an information theoretic decomposition criterion and graph theoretic concepts. Evidence based on empirical studies indicates the suitability of the scheme for achieving an optimal multicast communication cost.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

The fat-tree is one of the most widely-used topologies by interconnection network manufacturers. Recently, it has been demonstrated that a deterministic routing algorithm that optimally balances the network traffic can not only achieve almost the same performance than an adaptive routing algorithm but also outperforms it. On the other hand, fat-trees require a high number of switches with a non-negligible wiring complexity. In this paper, we propose replacing the fat--tree by a unidirectional multistage interconnection network (UMIN) that uses a traffic balancing deterministic routing algorithm. As a consequence, switch hardware is almost reduced to the half, decreasing, in this way, the power consumption, the arbitration complexity, the switch size itself, and the network cost. Preliminary evaluation results show that the UMIN with the load balancing scheme obtains lower latency than fat--tree for low and medium traffic loads. Furthermore, in networks with a high number of stages or with high radix switches, it obtains the same, or even higher, throughput than fat-tree.

Fault tolerance assessment for hamming graphs based on r-restricted R-structure(substructure) fault pattern

Dynamic load balancing techniques prevents computer nodes from overloading unevenly while leaving other idle. It is considered as one of the most challenging topics in parallel computing. Moreover, it is essential for increasing the efficiency of highly parallel systems especially in solving multitask problems with unpredictable load estimates. Particularly, over each processor in the parallel systems and interconnection networks. This paper focuses on developing an efficient algorithm for load balancing on Hyper Hexa Cell (HHC) interconnection network, namely, HHCLB algorithm. Basically, the Dimension Exchange Method (DEM) approach is used in this paper to construct a new load balancing approach on the network of HHC interconnections. Thus, an algorithm was introduced and simulated using java threads, where the performance of the algorithm is evaluated both analytically and experimentally. The evaluation was in terms of various performance metrics, including, execution time, load balancing accuracy, communication cost. By implementing the proposed load balancing algorithm to the HHC network, a high degree of accuracy and minimal execution time was achieved. It is important to highlight that the algorithm recorded small gap between the execution time for small number of processors and large number of processors. For instance, the algorithm achieved 0.14 seconds for balancing the load of 6 processors while 0.59 seconds for balancing the load of 3072 processors. This proves how effective the algorithm is in balancing the load for different network sizes from small to large number of processors, with a slight difference in execution time.

The topology of interconnection networks plays a key role in the performance of parallel computing systems. A new interconnection network called exchanged crossed cube (ECQ) is proposed and analyzed in this paper. We prove that ECQ has the better properties than other variations of the basic hypercube in terms of the smaller diameter, fewer links, and lower cost factor, which indicates the reduced communication overhead, lower hardware cost, and more balanced consideration among performance and cost. Furthermore, it maintains several attractive advantages including recursive structure, high partitionability, and strong connectivity. Furthermore, the optimal routing and broadcasting algorithms are proposed for this new network topology.

The author presents a solution to the previously unsolved problem of how to construct an array processor with N processing elements, N memory modules, and an interconnection network that allows parallel access and alignment of rows, columns, diagonals, contiguous blocks, and distributed blocks of N*N arrays. The solution leads to an array processor that is both simple and efficient in two critical respects: the memory system uses the minimum number of memory modules to achieve conflict-free memory access and is able to compute N addresses with O(log N) logic gates in O(1) time. The interconnection network is multistage with O(N log N) logic gates, and it can align any of these data vectors for store/fetch, as well as for subsequent processing with a single pass through the network. >

Fault-tolerance has been the focus of attention recently in the research of parallel processing and computer networking. A fault-tolerant routing algorithm should guarantee the delivery of messages in the presence of faulty components. In this paper, we present a comparative performance study of seven prominent fault-tolerant routings in 2-D wormhole-switched tori. The routing algorithms here are coupled with the Software-Based routing scheme which supports dynamic fault-model, enabling the network to remain fully operational at all times. The performance measures studied here are the throughput and average message latency. Results obtained through simulation suggest two classes of presented routing schemes as high performance candidates in most faulty networks.