A New Recursive Trigonometric Technique for FPGA-Design Implementation

Chapter 10 - Silicon Virtual Prototyping for FPGAs

This study presents the detailed design and analysis of a new memristor-based look-up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N-type metal-oxide-semiconductor transistors for row access. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand-by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit-level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non-volatile LUT outperforms existing static random access memory cell-based LUTs in terms of performance.

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuit's functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Many watermarking techniques for intellectual property (IP) protection are not resilient to tampering or removal attacks, especially for field programmable gate array (FPGA)-based IP cores. If attacked, the damaged watermarks cannot provide sufficient evidence in front of a court. To address this issue, the authors present a signature restoration scheme. The thought of secret sharing is introduced to share the signature into small watermarks. These watermarks are encoded with Reed-Solomon (RS) codes and embedded into unused lookup tables (LUTs) of used slices. Unlike most of existing techniques, the proposed scheme can restore the signature only by extracting parts of watermarks. So, it is tolerant to some damaged watermarks caused by removal attacks. The experiments show that the proposed scheme incurs no extra hardware resource and timing overhead. The robustness against attacks is much better by comparing to other schemes.

Chapter 8 - Design Simulation

These days, computer-based image registration techniques are increasingly being used in the area of medical imaging as they offer significant benefits for aligning different images together and for visualizing their combined images. However, these techniques require an enormous amount of computation time due to the high resolution and complex nature of the medical images. We propose to alleviate this problem by using a dedicated Network-on-Chip (NoC)-based hardware platform for image registration. This paper describes a novel technique for field-programmable gate array (FPGA) implementation of the B-Spline-based free form deformation (FFD) algorithm, i.e., a widely used algorithm for modeling geometric shapes in a computerized environment. For performance enhancement, we have utilized a lightweight circuit-switched NoC architecture, which is adaptable to most FPGAs. The design description is captured in the Verilog language and implemented using the Xilinx XC2v6000 device at 37[Formula: see text]MHz. The proposed design is parameterizable at the compile time and supports a wide range of the image resolutions and computational precisions. The experimental results have shown a significant improvement in performance when compared with the other existing hardware implementations of the B-spline-based FFD algorithm.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation.

Since decades, CORDIC (Coordinate Rotational Digital Computer) has been drawing attention as an arithmetic unit in the field of signal and image processing, communication system and robotics due to its low hardware complexity to compute linear, trigonometric and transcendental functions. Because of increased demand of high dynamic range in the aforesaid application, the floating point CORDIC is an obvious choice instead of fixed point arithmetic. To the knowledge of authors, only up to double precision CORDIC's are reported in literatures which are limited to a dynamic range of 2-1023 to 21024 and have accuracy up to 13 decimal digits, but these existing CORDIC are also not enough to support the high dynamic range of values to be computed for aforesaid functions. Hence, authors in this paper have proposed a new quadruple floating point CORDIC architecture which have dynamic range of 2-16383 to 216384 and are accurate up to 22 decimal digit. This architecture could meet the demand of present and future dynamic range. This proposed design is coded and simulated using Verilog HDL and synthesized using XST tool, targeting a commercially available FPGA device XCVLX110T-IFF1136. Further, the hardware utilization with its timing and power performance are reported in this paper.

Wireless mobile receivers and hand-held terminals have experienced tremendous growth. Especially, DAMPS (Digital American Mobile Phone System) has a tremendous market share in the cellular phone community. Mobile receiver designers feel the need to keep the cost of design low while maintaining a high performance, and to have a digital sub-system which uses DSP algorithms to provide immunity to multipath fading problem. A novel approach for VLSI realization of a reduced complexity of CORDIC (coordinate rotation digital computer) algorithm for DAMPS or a digital IF-sampled receiver is presented. It is intended to be suitable for the inexpensive realization of a demodulator, which is part of the D-AMPS modem within a VLSI chip. The reduced complexity CORDIC algorithm offers several advantages. First, it only uses one barrel shifter compared to the method of Chen, McDanell, Boytim and Pogue (see Proceedings IEEE Globecom, Singapore, 1995) with two barrel shifters. Also, the barrel shifter only needs to provide even shifts in the algorithm. Second, with a small input data, it can avoid the numerical problem. The scaling factors can be computed at the end of the CORDIC iterations instead of at every iteration. Overall, the algorithm is computationally efficient and conceptually simple with half complexity of previous schemes.

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

Stereo vision has become a very interesting sensing technology for robotic platforms. It offers various advantages, but the drawback is a very high algorithmic effort. Due to the aptitude of certain non-parametric techniques for field programmable gate array (FPGA) based stereo matching, these algorithms can be implemented in highly parallel design while offering adequate real-time behavior. To enable the provision of color images by the stereo sensor for object classification tasks, we propose a technique for extending the rank and the census transform for increased robustness on gray scaled Bayer patterned images. Furthermore, we analyze the extended and the original algorithmspsila behavior on image sets created in controlled environments as well as on real world images and compare their resource usage when implemented on our FPGA based stereo matching architecture.

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

We propose a method to simulate impairments caused by the nonideal analog parts of the transmitter-receiver. They include for example a high-power amplifier (HPA), mixers, and oscillators. The major advantage in our approach is that the model parameters are adjustable and the system works in real time in the digital domain. Conventional methods have either not been real time, or they have been implemented with analog circuits. The HPA model is implemented with the coordinate rotation digital computer (CORDIC) algorithm for rectangular to polar translations. A look-up table (LUT) is used for AM/AM and AM/PM distortion. To minimize the size of the LUT we have used cubic spline interpolation. For phase noise of the oscillators we propose a simple rotation mode CORDIC implementation that does not need any complex multiplication. Only one field-programmable gate array (FPGA) circuit is needed to implement the power amplifier and phase noise models.

Digital watermarking is an innovative technique for intellectual property protection (IPP) of Field Programmable Gate Array (FPGA) designs. However, many of these techniques usually need manually extract marks from binary bit-files by the FPGA tool or exhaustive search to find out marks in the design, which results in inefficiency of the watermark verification. This paper presents a method to fast verify the authorship through extracting the content of the watermarked lookup tables from a binary bit-file. We demonstrate the proposed method on several Xilinx Virtex-II devices, and experimental results on the watermarked designs from the IWLS 2005 benchmarks show that the verification of authorship has high efficiency.