Design and Implementation of Quadruple Floating-Point CORDIC

Digital communication plays a vital role in today’s communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna with fully programmable circuits having modulators and de-modulators. It may also end with hardware complexities. In order to overcome such complexities, a universal modulator is designed with an efficient iterative method named as CORDIC algorithm in prior methods. Although, the CORDIC (Coordinate Rotation Digital Computer) algorithm works efficiently, it leads to computational as well as memory complexities. Additionally it creates a need for latency reduction strategy. Therefore, to compete with all these issues faced with the prior method, we proposed an amended CORDIC algorithm in universal modulator working with the principle of the harmonized Stone–Weierstrass theorem. In addition, the Newton–Raphson method and Remz algorithm are introduced here to reduce the memory complexity by doubling the number of iterations and to select the best carrier signal, respectively. Thus, our proposed work effectively unravels all the notorious issues caused with the conventional CORDIC algorithm and the proposed universal modulator is implemented in Xilinx.

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

Rotation is a basic operation for image processing, and the complexity of its computation is considered as the key problem of the implementation of real-time visual system. This paper proposes a novel architecture based on modified compensated CORDIC and bilinear interpolation algorithms in a recursive and folded way. The proposed modified compensated CORDIC algorithm compensates the scale factor in parallel with angle rotations, expands the convergence range to entire 2/spl pi/ and avoids pre- and post- rotations. The detailed architecture for image rotation is modeled by Verilog and implemented in Xilinx FPGA. Experiment results show that the proposed CORDIC algorithm has the lowest computational complexity and the architecture for real-time image rotation has lower hardware cost and power consumption.

In response to the limitations of insufficient reconfigurability and excessive hardware resource overhead associated with traditional FFT circuits in multi-standard signal processing scenarios, this paper proposes a reconfigurable mixedradix FFT circuit design grounded in the CORDIC (Coordinate Rotation Digital Computer) algorithm. This design employs a hybrid basis $(2 / 3 / 4 / 5)$ decomposition structure, enabling the reconfigurable computation of FFTs with varying point counts through the dynamic configuration of computational units. An enhanced CORDIC algorithm is implemented in the rotation factor generation module, where an optimized set of rotation angles is utilized. This method effectively reduces hardware resource consumption and latency while ensuring computational accuracy. Simulation and experimental results conducted on an FPGA platform demonstrate that the design achieves a computational signal-to-noise ratio (SNR) of at least 60 dB, thereby meeting the precision requirements of most communication systems. When compared to similar FFT circuits, this design significantly decreases hardware resource utilization while maintaining comparable computational speed, resulting in an approximate power savings of $\mathbf{4 4\%}$. Keywords-Mixed-Radix FFT CORDIC Reconfigurable

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

Some data streaming applications make use of digital signal processing (DSP). The DSP algorithms include transcendental functions like trigonometry, inverse trigonometry, logarithms, exponentials, and other functions in addition to the basic arithmetic operations of multiplication and division. By modifying a few simple parameters, it is relatively simple to generate a large range of functions, including logarithmic, exponential, and trigonometric ones. Since the CPU needs around n rounds to process n bits of incoming data, the CORDIC radix-2 causes a substantial amount of latency. Therefore, radix-4 (which is radix-4 plus one) and radix-8 (which is radix-8 plus one) may be used to reduce the amount of time needed for the calculation. As a result, the total iterations drop from n/2 to n/4. As simulated and synthesized, it was shown that the radix-8 design had a significantly higher power consumption, with greater throughput than the radix-2 and radix-4 Coordinate Rotational Digital Computer (CORDIC) designs with an additional area overhead. The new algorithm also reduces the amount of twiddle elements to a minimum while also simplifying the address generating process. A novel approach makes integrating FFT processors on single chips much easier. This approach is demonstrated to be notably efficient in procedures such as SVD or matrix triangularization, in which the calculation of the rotation angle is necessary.

COordinate Rotation DIgital Computer (CORDIC) is an effective method that is used in digital signal processing applications for computing various trigonometric, hyperbolic, linear, and transcendental functions. This paper presents the theoretical basis and practical implementation of circular (sine-cosine) CORDIC-based generator. Synthesis results of this generator based on Altera Stratix III FPGA (EP3SL340F1517C2) using Quartus II version 9.0 show that the proposed hybrid FPGA architecture significantly reduces latency (42% reduction) with a small area overhead, compared to the conventional version. The proposed algorithm has been simulated for sine and cosine function evaluation, and it has been verified that the accuracy is comparable with conventional algorithm.

Digital Down Conversion (DDC) is a fundamental process in software defined radio (SDR) and digital communications, which transforms intermediate frequency (IF) signals into baseband signals. In conventional DDC designs, multipliers and look-up tables are generally employed, both of which tend to increase hardware size and power consumption. In this paper we present a Dual-Mode CORDIC-Based DDC architecture which uses the CORDIC (Coordinate Rotation Digital Computer) algorithm to eliminate multipliers. This novel architecture combines a CORDIC-based Numerically Controlled Oscillator (NCO), a CORDIC mixer, and a Cascaded Integrator-Comb (CIC) filter with a finite impulse response (FIR) com pentation filter. The NCO provides two precision modes - an 8-stage low-latency mode for speed and a 16-stage high precision mode for accuracy, giving runtime reconfigurability according to design requirements. Simulations and analysis show that the design gives highly accurate frequency translation, is efficient in hardware utilization and fully eliminates the use of digital signal processing (DSP) blocks. Overall, the architecture proposed offers a low-power, low-cost, and recon figural solution ideal for modern SDR-based applications and flexible digital signal processing systems.

Typical digital cameras exhibit a limitation regarding the dynamic range of the scene radiance they can capture. High Dynamic Range (HDR) imaging refers to methods and systems that aim to generate images that exhibit higher dynamic range between the lightest and the darkest parts of the an image. A typical approach for generating HDR images is exposure bracketing where multiple frames, each one with a different exposure setting, are captured and combined to a HDR image of the scene. The large number of images that exposure bracketing requires often leads to motion artefacts that limit the visual quality of the resulting HDR image. In this work, we propose a novel approach in HDR imaging that significantly reduces the necessary number of images. In our proposed system, we employ the notion of random exposure where each pixel of a single frame collects light for a random amount of time. By collecting a small number of such images, the full sequence of low dynamic range images can be reconstructed and subsequently used for HDR generation. The problem is solved by casting the reconstruction of the sequence as a nuclear norm minimization problem following the premises of the recently proposed theory of Matrix Completion. Experimental results suggest that the proposed method is able to reconstruct the sequence from as low as 20% of the images that traditional techniques require with minimal reduction in image quality.

High dynamic range (HDR) imaging is a technique that allows an extensive dynamic range of exposures, which is important in image processing, computer graphics, and computer vision. In recent years, there has been a significant advancement in HDR imaging using deep learning (DL). This study conducts a comprehensive and insightful survey and analysis of recent developments in deep HDR imaging methodologies. We hierarchically and structurally group existing deep HDR imaging methods into five categories based on (1) number/domain of input exposures, (2) number of learning tasks, (3) novel sensor data, (4) novel learning strategies, and (5) applications. Importantly, we provide a constructive discussion on each category regarding its potential and challenges. Moreover, we review some crucial aspects of deep HDR imaging, such as datasets and evaluation metrics. Finally, we highlight some open problems and point out future research directions.

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Feature Point (FP) detection is a fundamental step in computer vision tasks. Although FP detectors are mostly designed to support Low Dynamic Range (LDR) images as input, interest in High Dynamic Range (HDR) images has increased recently due to their higher precision to register overexposed and underexposed areas in an image. As the detection of FPs is strongly dependent on the illumination of the scene, HDR images have the potential to be more robust than LDR images during FP detection. Known FP detectors, however, do not use the full potential of HDR images. In addition, few works have evaluated the performance of HDR images in this context. In this paper, we propose a modification of FP detectors aiming to improve FP detection on HDR images. To this end, we design a local mask based on the Coefficient of Variation (CV) of sets of pixels, creating thus a new step in FP detection. We compare our approach with popular FP detection methods using a standard evaluation metric, Repeatability Rate (RR) of FPs, and also Uniformity as a proposed new criterion. A dataset of images from scenes affected by camera transformations and substantial illumination changes was used as input. Experimental results show that our proposed algorithms give better Uniformity and RR in most HDR images from the dataset when compared to standard FP detectors. Moreover, they indicate that HDR images present a great potential to be explored in applications that rely on FP detection.

High dynamic range (HDR) images are becoming pervasive due to capturing or rendering of a wider range of luminance, but their special display equipment is difficult to be popularized because of high cost and technological problem. Thus, HDR images must be adapted to the conventional display devices by applying tone mapping (TM) operation, which puts forward higher requirements for intellectual property protection of HDR images. As the robustness presents regional diversity in the low dynamic range (LDR) watermarked image after TM, which is different from the traditional watermarking technologies, a concept of watermarking activity is defined and used to distinguish the essential distinction of watermarking between LDR image and HDR image in this paper. Then, a novel robust HDR image watermarking algorithm is proposed against TM operations. Firstly, based on the hybrid processing of redundant discrete wavelet transform and singular value decomposition, the watermark is embedded by modifying the structure information of the HDR image. Distinguished from LDR image watermarking, the high embedding strength can cause more obvious distortion in the high brightness regions of HDR image than the low brightness regions. Thus, a perceptual brightness mask with low complexity is designed to improve the imperceptibility further. Experimental results show that the proposed algorithm is robust to the existing TM operations, with taking into account the imperceptibility and embedded capacity, which is superior to the current state-of-art HDR image watermarking algorithms.

Tone-mapping-operators (TMOs) provide a useful means for converting high dynamic range (HDR) images to low dynamic range (LDR) images so that they can be viewed on standard displays, but this may influence the visual quality of experience (QoE) of the end-user. There is a need to understand the impact of TMOs to inform the choice of TMO algorithms for different displays, especially for small-screen-devices (SSDs) such as those used in mobile phones. This is important, as mobile devices are becoming the primary means of consuming multimedia contents. However, few studies have been undertaken to assess the impact of TMOs and viewing devices (especially SSDs) on the visual QoE of the user when using. In this chapter, we evaluate subjectively and objectively, the commonly used TMOs in different displays and resolutions for colour and grey-scale HDR images. Our results show that viewing devices have an influence on the TMOs performance, suggesting the need for a careful choice of TMO to enhance the viewing-QoE of the end-user. As expected, the higher resolution, the better HDR-image quality. Surprisingly, there was no significant difference between the Mean of Opinion Score (MOS) scores for colour and grey-scale images in SSDs. The device and TMOs affect QoE for colour and grey HDR-image equally. We found Shannon entropy (SE) to be a good objective measure of quality for colour and grey HDR images, suggesting that entropy may find use in automated HDR quality control assessment schemes, while; HDR-VDP-2 is a good objective measure for colour HDR image only.

Recently, visual representations using high dynamic range (HDR) images become increasingly popular, with advancement of technologies for increasing the dynamic range of image. HDR image is expected to be used in wide-ranging applications such as digital cinema, digital photography and next generation broadcast, because of its high quality and its powerful expression ability. HDR imaging technologies will spread its sphere of influence in imaging industry. In this paper, we review the state-of-the-art studies and the trends of the HDR imaging, in terms of the following three points: (1) HDR imaging sensor and HDR image generation techniques as image acquisition technologies, (2) encode method of HDR images for efficient transmission and storage, (3) human visual system issues associated with reproduction of HDR image.