Energy Efficient Quality Tunable CORDIC for DSP Applications on Battery Operated Portable Devices

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation.

Since decades, CORDIC (Coordinate Rotational Digital Computer) has been drawing attention as an arithmetic unit in the field of signal and image processing, communication system and robotics due to its low hardware complexity to compute linear, trigonometric and transcendental functions. Because of increased demand of high dynamic range in the aforesaid application, the floating point CORDIC is an obvious choice instead of fixed point arithmetic. To the knowledge of authors, only up to double precision CORDIC's are reported in literatures which are limited to a dynamic range of 2-1023 to 21024 and have accuracy up to 13 decimal digits, but these existing CORDIC are also not enough to support the high dynamic range of values to be computed for aforesaid functions. Hence, authors in this paper have proposed a new quadruple floating point CORDIC architecture which have dynamic range of 2-16383 to 216384 and are accurate up to 22 decimal digit. This architecture could meet the demand of present and future dynamic range. This proposed design is coded and simulated using Verilog HDL and synthesized using XST tool, targeting a commercially available FPGA device XCVLX110T-IFF1136. Further, the hardware utilization with its timing and power performance are reported in this paper.

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign‐precomputation‐based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z ‐datapath, and involves precomputation of the direction of rotation for each micro‐rotation angle. The approach involves selecting the optimal micro‐rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro‐rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T‐3FBG676 Kintex‐7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice‐delay product and power‐delay product compared to recent designs. An application of approximate rotation to Hough transform‐based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

The Coordinate Rotation Digital Computer (CORDIC) algorithms provide a VLSI hardware technique for computing the inverse tangents and vector rotations needed by many matrix decomposition algorithms. A novel simplified CORDIC processor composed of floating-point data paths with a fixed-point angle calculation is proposed. This hybrid processor possesses sufficient accuracy for matrix computations such as the QRD, eigenvalue decomposition, and the singular value decomposition. The simplified structure allows for efficient VLSI implementation. >

With the wide use of various image altering tools, digital image manipulation becomes very convenient and easy, which makes the detection of image originality and authenticity significant. Among various image tampering detection tools, double JPEG image compression detector, which is not sensitive to specific image tampering operation, has received large attention. In this paper, we propose an improved double JPEG compression detection method based on noise-free DCT (Discrete Cosine Transform) coefficients mixture histogram model. Specifically, we first extract the block-wise DCT coefficients histogram and eliminate the quantization noise which introduced by rounding and truncation operations. Then, for each DCT frequency, a posterior probability can be obtained by solving the DCT coefficients mixture histogram with a simplified model. Finally, the probabilities from all the DCT frequencies are accumulated to give the posterior probability of a DCT block being authentic or tampered. Extensive experimental results in both quantitative and qualitative terms prove the superiority of our proposed method when compared with the state-of-the-art methods.

This paper presents new fast full search motion estimation (ME) algorithms using discrete cosine transform (DCT) coefficients as a gradient magnitude. The proposed algorithms use intra DCT coefficients to arrange the matching scan order. The proposed algorithm 1 uses some of DCT coefficients based on the relationship between gradient magnitude and DCT coefficients, and the proposed algorithm 2 uses all of DCT alternating current (AC) coefficients in order to predict the fluctuation of a block. The proposed algorithms significantly reduce the computational complexity of the conventional algorithm while maintaining the visual quality of video.

Some data streaming applications make use of digital signal processing (DSP). The DSP algorithms include transcendental functions like trigonometry, inverse trigonometry, logarithms, exponentials, and other functions in addition to the basic arithmetic operations of multiplication and division. By modifying a few simple parameters, it is relatively simple to generate a large range of functions, including logarithmic, exponential, and trigonometric ones. Since the CPU needs around n rounds to process n bits of incoming data, the CORDIC radix-2 causes a substantial amount of latency. Therefore, radix-4 (which is radix-4 plus one) and radix-8 (which is radix-8 plus one) may be used to reduce the amount of time needed for the calculation. As a result, the total iterations drop from n/2 to n/4. As simulated and synthesized, it was shown that the radix-8 design had a significantly higher power consumption, with greater throughput than the radix-2 and radix-4 Coordinate Rotational Digital Computer (CORDIC) designs with an additional area overhead. The new algorithm also reduces the amount of twiddle elements to a minimum while also simplifying the address generating process. A novel approach makes integrating FFT processors on single chips much easier. This approach is demonstrated to be notably efficient in procedures such as SVD or matrix triangularization, in which the calculation of the rotation angle is necessary.

A low power discrete cosine transform (DCT) architecture is presented. It is implemented through Loffler DCT based on the coordinate rotation digital computer (Cordic) algorithm and the canonical sign-digital (CSD) multiplier-less architecture. The synthesis results show that the proposed 8-point one-dimensional DCT architecture consumes lower power and smaller area.

The performance of neuromorphic systems is primarily determined by the interplay between neurons and learning models. Achieving an optimal trade‐off between their computational accuracy and hardware implementation complexity represents a fundamental challenge in pursuing brain‐like neural network designs. This paper introduces a two‐stage pipelined design for spiking neural networks (SNNs) utilizing an adaptive coordinate rotation digital computer (CORDIC) algorithm. Our approach begins with leveraging the adaptive CORDIC method to efficiently approximate square‐term computations in the Izhikevich neuron model, as well as the exponential calculations involved in the spike timing‐dependent plasticity (STDP) algorithm. In addition, a low‐overhead hardware circuit was developed to record the timing of spike firing. FPGA‐based online learning is subsequently implemented on an adaptive CORDIC Izhikevich neuron network. Performance is assessed regarding resource utilization, power efficiency, operational frequency, and computational accuracy, and the results are benchmarked against the latest advancements in the field. This design utilizes 199 look‐up tables (LUTs) and 336 registers per neuron, achieving a remarkably low power consumption of 4.6 mW. It operates at a maximum frequency of 434.7 MHz, with an average computation latency of 74 ns for a single MPI (message passing interface). Additionally, the STDP mechanism attains a peak operating frequency of 287.2 MHz. These results confirm the precision of the adaptive CORDIC‐based SNN, highlighting its superior performance in high‐speed operation, energy efficiency, and minimal area. Owing to these characteristics, the proposed design is particularly well‐suited for resource‐constrained, latency‐sensitive applications such as edge computing, autonomous robotics, and real‐time sensor processing.