Low-Power High-Modularity Architecture for 8-Point DCT Computation

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

A low power discrete cosine transform (DCT) architecture is presented. It is implemented through Loffler DCT based on the coordinate rotation digital computer (Cordic) algorithm and the canonical sign-digital (CSD) multiplier-less architecture. The synthesis results show that the proposed 8-point one-dimensional DCT architecture consumes lower power and smaller area.

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

Demand of high quality image and video increases day by day. Quality is directly proportional to data size so there is need of compression. Discrete Cosine Transform (DCT) very popular in Latest Video codec standards because of its energy compaction and decorrelation properties. High Efficiency Video Codec (HEVC) is latest video codec technique which uses 4×4 to 32×32 basis vector for transformation. We implemented Input Adder Unit (IAU), Shift and Add Unit (SAU) and Output Adder Unit (OAU) of 1D and 2 D DCT of 4×4 and 8×8. This paper proposes SAU which has less Area Delay Product (ADP). Implementation is performed on Xilinx Spartan-3E FPGA, The proposed Hardware SAU takes 110 (4×4), 321(8×8) LUTs and 70(4×4), 212(8×8) slice registers with 494.56(4×4), 1143.216(8×8) ADP. By implementing our SAU into 1D as well as 2D DCT it takes 321 LUTs, 212 slice registers, 1410.4 ADP for 4×4 1D DCT architecture 1477 LUTs, 922 slice registers, 6489.9 ADP for 8×8 1D DCT architecture, 1284 LUTs, 847 slice registers, 5641.8 ADP for 4×4 2D DCT architecture 86 LUTs, 58 slice registers, 368.3 ADP for 8×8 2D DCT architecture. We also proposed Flexible Architecture from which User can switch between 4×4 and 8×8 Architecture according to application.

The Discrete Cosine Transform (DCT) is one of the most widely used techniques of transforms in digital signal processing. It is the main algorithm in image and video coding systems. In this paper, we propose an algorithm which generates enhanced Cordic based Loeffler DCT architectures for angle’s precision degrees ranging from 10−1 to 10−7. High level PSNR, area and power estimators have been proposed to make a trade-off between consumption and image quality. An optimal architecture has been retained for its low complexity, low power and high PSNR. The complexity of this architecture is the lowest among the conventional DCT architectures even the BinDCT which is a reference in terms of reduced complexity. The selected architecture has also the closest PSNR to the reference Loeffler-DCT architecture without a substancial loss of power.

COrdinate Rotation DIgital Computer (CORDIC) is commonly utilized for the computation of cosine/sine i.e., the trigonometric functions, singular value decomposition, in digital signal processing (especially in image/video processing), etc. This paper introduces an energy efficient quality tunable CORDIC architecture that computes the cosine/sine values of any required angle in real-time, and is thus well suited for real time DSP applications, especially for image or video processing applications. The proposed architecture reduces the latency and overcomes data dependency by simultaneously performing all the five iterations, that may vary depending upon the desired energy efficiency. The novelty of this architecture is that, desired quality can be achieved by selecting one out of the available three modes. In order to assess the efficacy of the suggested architecture, some benchmark images are processed using the Discrete Cosine Transform (DCT) coefficients obtained via the proposed design. Energy saving is achieved at the cost of slight acceptable degradation in the output image quality. Further, the simulation results show that the proposed architecture is 92.3%, 2.8% and 49.08% more energy efficient than the existing basic, scale-free and lookahead CORDIC architectures, respectively.

The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

The discrete cosine transform (DCT) and its inverse (IDCT) are widely used in image and video compression standards. In this paper, we propose a novel unified architecture for DCT and IDCT based on adaptive recoding coordinate rotation digital computer (ARC). The proposed architecture requires two types of ARC rotators. In addition, an efficient adder and shifter-based scale factor approximation is used in the proposed architecture. To verify the function and evaluate the performance, the proposed architecture is validated on a Virtex 5 FPGA development platform. Under DCT-only mode, compared with the proposed architecture, a state-of-the-art DCT architecture uses 12% more hardware resources, increases the critical path delay by 7.12%, consumes 10.1% more power and decreases 4.8 dB in PSNR. Under DCT/IDCT mode, the latest unified DCT/IDCT architecture has a factor of 2.17-fold in latency, needs 74.9% more hardware resources and dissipates 52.5% more power when compared to the proposed architecture. In addition, PSNR of the proposed architecture is better by 2 dB.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.

Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE Field Programmable Gate Array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.

The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation.

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.