Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic

This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or subtractors, one small ROM module, a barrel shifter, and ((N-1)/2)+1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.

The paper describes the design of 2D-discrete cosine transform (DCT) which is widely used in image and video compression algorithms. The objective of this paper is to design a fully parallel distributed arithmetic (DA) architecture for 2D-dimensional DCT to be implemented on field programmable gate array (FPGA). DCT requires large amount of mathematical computations including multiplications and accumulations. The multipliers consume increased power and area; hence multipliers are completely discarded in the proposed design. Distributed arithmetic is a method of modification at bit stream for sum of product or vector dot product to hide the multiplications. DA is very much suitable for FPGA designs as it reduces the size of a multiply and accumulate hardware. The speed is increased in the proposed design with the fully parallel approach. In this work, existing DA architecture for 2D-DCT and the proposed area efficient fully parallel DA architecture for 2D-DCT are realized. The simulation and synthesis is performed using Xilinx ISE.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

Demand of high quality image and video increases day by day. Quality is directly proportional to data size so there is need of compression. Discrete Cosine Transform (DCT) very popular in Latest Video codec standards because of its energy compaction and decorrelation properties. High Efficiency Video Codec (HEVC) is latest video codec technique which uses 4×4 to 32×32 basis vector for transformation. We implemented Input Adder Unit (IAU), Shift and Add Unit (SAU) and Output Adder Unit (OAU) of 1D and 2 D DCT of 4×4 and 8×8. This paper proposes SAU which has less Area Delay Product (ADP). Implementation is performed on Xilinx Spartan-3E FPGA, The proposed Hardware SAU takes 110 (4×4), 321(8×8) LUTs and 70(4×4), 212(8×8) slice registers with 494.56(4×4), 1143.216(8×8) ADP. By implementing our SAU into 1D as well as 2D DCT it takes 321 LUTs, 212 slice registers, 1410.4 ADP for 4×4 1D DCT architecture 1477 LUTs, 922 slice registers, 6489.9 ADP for 8×8 1D DCT architecture, 1284 LUTs, 847 slice registers, 5641.8 ADP for 4×4 2D DCT architecture 86 LUTs, 58 slice registers, 368.3 ADP for 8×8 2D DCT architecture. We also proposed Flexible Architecture from which User can switch between 4×4 and 8×8 Architecture according to application.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE Field Programmable Gate Array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.

In this paper, we present a low-power distributed arithmetic (DA) architecture. In a DA architecture, a memory is employed to store linear combinations of coefficients. The probability distribution of addresses to the memory is usually not uniform because of temporal correlation in the input. We present a rule governing this probability distribution and use it to partition the memory such that the most frequently accessed locations are stored in the smallest memory. Power dissipation is reduced because accesses to smaller memories dissipate less power. Experimental results with an 8-tap filter with 8 bits of data precision result in a 32% power reduction in the memory. A 28% power reduction was obtained by just detecting accesses to the two most frequently accessed locations (0/spl times/00 and 0/spl times/FF), which is a strong argument for using the techniques proposed in this paper.

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

The Discrete Cosine Transform (DCT) is one of the most widely used techniques of transforms in digital signal processing. It is the main algorithm in image and video coding systems. In this paper, we propose an algorithm which generates enhanced Cordic based Loeffler DCT architectures for angle’s precision degrees ranging from 10−1 to 10−7. High level PSNR, area and power estimators have been proposed to make a trade-off between consumption and image quality. An optimal architecture has been retained for its low complexity, low power and high PSNR. The complexity of this architecture is the lowest among the conventional DCT architectures even the BinDCT which is a reference in terms of reduced complexity. The selected architecture has also the closest PSNR to the reference Loeffler-DCT architecture without a substancial loss of power.

This paper presents a new scalable architecture for Discrete Cosine Transform (DCT). In contrast to the conventional DCT architecture, the proposed architecture reduces the number of constant cosine terms using the matrix transposition and symmetry property. This in turn, considerably reduces the computation time. The architecture is scalable and it can be extended to support any transform length. The architecture was validated on Xilinx Vertex-4 FPGA.

The author proposes an efficient parallel adder based design for the one-dimensional (1-D) discrete cosine transform (DCT). A new algorithm is developed that exploits the merits of cyclic convolution to facilitate the realisation of a 1-D any-length DCT using parallel adders. Based on this algorithm, the proposed design possesses the advantages of low hardware cost, low input/output (I/O) cost, high computing speed, and high flexibility in transform length. Considering an example using 16-bit coefficients, the proposed design can save about 58% and 80% of the gate area, as compared with the distributed arithmetic (DA)-based designs, for the 64 and 128 transform lengths, respectively.

A low power discrete cosine transform (DCT) architecture is presented. It is implemented through Loffler DCT based on the coordinate rotation digital computer (Cordic) algorithm and the canonical sign-digital (CSD) multiplier-less architecture. The synthesis results show that the proposed 8-point one-dimensional DCT architecture consumes lower power and smaller area.

The discrete cosine transform (DCT) and its inverse (IDCT) are widely used in image and video compression standards. In this paper, we propose a novel unified architecture for DCT and IDCT based on adaptive recoding coordinate rotation digital computer (ARC). The proposed architecture requires two types of ARC rotators. In addition, an efficient adder and shifter-based scale factor approximation is used in the proposed architecture. To verify the function and evaluate the performance, the proposed architecture is validated on a Virtex 5 FPGA development platform. Under DCT-only mode, compared with the proposed architecture, a state-of-the-art DCT architecture uses 12% more hardware resources, increases the critical path delay by 7.12%, consumes 10.1% more power and decreases 4.8 dB in PSNR. Under DCT/IDCT mode, the latest unified DCT/IDCT architecture has a factor of 2.17-fold in latency, needs 74.9% more hardware resources and dissipates 52.5% more power when compared to the proposed architecture. In addition, PSNR of the proposed architecture is better by 2 dB.

This paper presents a brief on the implementation of reconfigurable shared LUT (look-up-table) based Distributed Arithmetic (DA) for the higher order finite-impulse response (FIR) filters whose filter coefficients can be changed during run time. In this architecture all the multipliers and adders are replaced by the register banks, multiplexers and the shifters. The throughput rate of the design is increased by having shared LUTs instead of ROM in the DA FIR filter architecture. By implementing this concept in ASIC, the area, area delay product (ADP), minimum cycle period (MCP) and energy per sample are reduced when compare with the conventional DA architecture. The architecture supports 95 MHz sampling frequency.

The design of DCT (discrete cosine transform) circuits for HDTV (high-definition television) applications is addressed. Based on previous works on CCIR video image coding, several architectural solutions are presented and then compared. An optimization taking into account the potentials of present-day technologies and progress in arithmetic implementation and architecture makes it possible to implement a real-time DCT for HDTV implementation in roughly 40 mm/sup 2/ (0.8- mu m CMOS). >