Fast and Multiplierless Integer DCT for HEVC

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE Field Programmable Gate Array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard ‘Lena’ image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.

Image interpolation, with its image magnifying abilities, is an image processing operation of increasing importance in the fields of biology and medicine. In this paper, we present a novel image interpolation technique that utilizes the discrete cosine transform (DCT). The DCT provides for a decrease in border effects, and improves the processing speed. The advantages of this technique over the traditional Fourier-transform-based techniques stem from basic properties of DCT that it is a non-periodic, real (non-complex) transform with excellent energy compaction in the transform domain. In fact, the DCT's energy compaction property is next only to Karhunen-Loeve transform in the mean squared sense on an ensemble of images (Jain, 1989). In addition, DCT allows interpolation of small volumes (e.g., 8/spl times/8/spl times/8) which is not easily possible with an FFT-based method. Therefore, the present technique is better suited for applications such as a real-time 3D interactive maximum intensity projection, real-time 2-D image magnifier etc. More importantly, the technique can be used for the bandlimited interpolation of any digitally acquired data to minimize partial voluming artifact.

The Discrete Cosine Transform (DCT) is one of the most widely used techniques of transforms in digital signal processing. It is the main algorithm in image and video coding systems. In this paper, we propose an algorithm which generates enhanced Cordic based Loeffler DCT architectures for angle’s precision degrees ranging from 10−1 to 10−7. High level PSNR, area and power estimators have been proposed to make a trade-off between consumption and image quality. An optimal architecture has been retained for its low complexity, low power and high PSNR. The complexity of this architecture is the lowest among the conventional DCT architectures even the BinDCT which is a reference in terms of reduced complexity. The selected architecture has also the closest PSNR to the reference Loeffler-DCT architecture without a substancial loss of power.

This paper introduces a cepstral approach for the detection of landmines from acoustic images. This approach is based on transforming the 2D landmine images to 1D signals using a spiral scan to make object pixels as close as possible to each other after the scan. The Mel-frequency cepstral coefficients (MFCCs) and polynomial shape coefficients are extracted from these 1D signals to form a database of features, which can be used to train a neural network. The discrete cosine transform (DCT) and the discrete wavelet transform (DWT) are also investigated in this paper for the possible extraction of features from these transforms of the original images and/or the original images themselves. The detection of landmines can be performed by extracting features from any new image with the same method used in the training phase. These features are tested with the neural network to decide whether a landmine exists or not. Experimental results show that, the proposed cepstral approach with features extracted from the 2D DCT are the most robust and reliable features in the detection process because of its strong energy compaction property.

A low power discrete cosine transform (DCT) architecture is presented. It is implemented through Loffler DCT based on the coordinate rotation digital computer (Cordic) algorithm and the canonical sign-digital (CSD) multiplier-less architecture. The synthesis results show that the proposed 8-point one-dimensional DCT architecture consumes lower power and smaller area.

The discrete cosine transform (DCT) and its inverse (IDCT) are widely used in image and video compression standards. In this paper, we propose a novel unified architecture for DCT and IDCT based on adaptive recoding coordinate rotation digital computer (ARC). The proposed architecture requires two types of ARC rotators. In addition, an efficient adder and shifter-based scale factor approximation is used in the proposed architecture. To verify the function and evaluate the performance, the proposed architecture is validated on a Virtex 5 FPGA development platform. Under DCT-only mode, compared with the proposed architecture, a state-of-the-art DCT architecture uses 12% more hardware resources, increases the critical path delay by 7.12%, consumes 10.1% more power and decreases 4.8 dB in PSNR. Under DCT/IDCT mode, the latest unified DCT/IDCT architecture has a factor of 2.17-fold in latency, needs 74.9% more hardware resources and dissipates 52.5% more power when compared to the proposed architecture. In addition, PSNR of the proposed architecture is better by 2 dB.

This paper presents a new scalable architecture for Discrete Cosine Transform (DCT). In contrast to the conventional DCT architecture, the proposed architecture reduces the number of constant cosine terms using the matrix transposition and symmetry property. This in turn, considerably reduces the computation time. The architecture is scalable and it can be extended to support any transform length. The architecture was validated on Xilinx Vertex-4 FPGA.

In this paper, a reconfigurable macro-pipelined (RMP) accelerator is proposed to speed up the Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute fixed-point or floating-point, one-dimensional or multi-dimensional DCT/IDCT according to different system requirements. The prototype is implemented on Xilinx ML605 experiment board with 64 PEs. It takes 64 cycles at 200MHz to complete an 8×8 2D DCT and gets a peak performance of 25.6 GFLOPS for the floating-point DCT. The excellent scalability of this architecture enables the accelerator to scale up to an extremely high performance.

The discrete cosine transform (DCT) is widely used in all transform-based image and video compression standards due to its well-known decorrelation and energy compaction properties for typical images. Many fast algorithms available for the DCT optimize various parameters such as additions and multiplications but they are input independent and thus require the same number of operations for any inputs. In this paper we study the benefits of input- dependent algorithms for the DCT which are aimed at minimizing the average computation time by taking advantage of the sparseness of the input data. Here, we concentrate on the inverse DCT (IDCT) part since typical input blocks will contain a substantial number of zeros. We show how to construct an IDCT algorithm based on the statistics of the input data, which are used to optimize the algorithm for the average case. We show how, for a given input and a correct model of the complexity of the various operations, we can achieve the fastest average performance.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We consider two novel representations and feature extraction schemes for automatic recognition of emotion related facial expressions. In one scheme facial landmark points are tracked over successive video frames using an effective detector and tracker to extract landmark trajectories. Features are extracted from landmark trajectories using Independent Component Analysis (ICA) method. In the alternative scheme, the evolution of the emotion expression on the face is captured by stacking normalized and aligned faces into a spatiotemporal face cube. Emotion descriptors are then 3D Discrete Cosine Transform (DCT) features from this prism or DCT & ICA features. Several classifier configurations are used and their performance determined in detecting the 6 basic emotions. Decision fusion applied to classifiers improved the recognition performance of best classifier by 9 percentage points. The proposed method was evaluated user independently on the Cohn-Kanade facial expression database and a state-of-the-art 95.34 % recognition performance is achieved.KeywordsFacial expression analysisspatiotemporal featuresface prism