FPGA Implementation of Image Rotation Using Modified Compensated CORDIC

The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (COordinate Rotation DIgital Computer) processor. In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes - one using adders in all the stages and another using multiplexers in the second and third stages. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed.

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign‐precomputation‐based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z ‐datapath, and involves precomputation of the direction of rotation for each micro‐rotation angle. The approach involves selecting the optimal micro‐rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro‐rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T‐3FBG676 Kintex‐7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice‐delay product and power‐delay product compared to recent designs. An application of approximate rotation to Hough transform‐based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

This work proposes a new rotation mode CORDIC algorithm, which considerably reduces the iteration number. It is achieved by combining several design techniques. Particularly, a new table-lookup recoding scheme for rotation angles and variable scale factors is developed to reduce the iteration numbers for rotation and scale factor compensation. By addressing the MSB parts of the residual rotation angles to a lookup table, two micro rotation angles are retrieved that in combination best matches the MSB parts. We also combine the leading-one bit detection operations for residual rotation angles, to skip unnecessary rotations. The resulting problems of variable scale factors are then solved by our previous fast decomposition and compensation algorithm (C.C. Li and S.G. Chen, in Proceedings of 1996 IEEE International Symposium Circuits and Systems, May 1996, Atlanta, USA, pp. 264–267s C.C. Li and S.G. Chen, in Proceedings of 1997 IEEE International Conference on Acoustic, Speech and Signal Processing, Munich, 1997, Germany, pp. 639–642). To further reduce the iteration number of scale factor compensation, we again apply the mentioned residual recoding technique and the leading-one bit detection scheme to the fast variable scale factor algorithm. Those techniques collectively reduce the iteration number significantly. Simulations show that in average the new design needs only 9.78 iterations to generate results with 22-bit accuracy, including all the iterations for rotations and scale factor compensations. Statistically, the total iteration number is less than n/2 for results with n-bit accuracy. The introduced extra table size is of the same order of magnitude as that for the angle set ltan−1 2−i, i e 0,1,…,nr, required by general CORDIC algorithms. The new recoding scheme can be applied to other elementary function such as division and square-root functions.

Some data streaming applications make use of digital signal processing (DSP). The DSP algorithms include transcendental functions like trigonometry, inverse trigonometry, logarithms, exponentials, and other functions in addition to the basic arithmetic operations of multiplication and division. By modifying a few simple parameters, it is relatively simple to generate a large range of functions, including logarithmic, exponential, and trigonometric ones. Since the CPU needs around n rounds to process n bits of incoming data, the CORDIC radix-2 causes a substantial amount of latency. Therefore, radix-4 (which is radix-4 plus one) and radix-8 (which is radix-8 plus one) may be used to reduce the amount of time needed for the calculation. As a result, the total iterations drop from n/2 to n/4. As simulated and synthesized, it was shown that the radix-8 design had a significantly higher power consumption, with greater throughput than the radix-2 and radix-4 Coordinate Rotational Digital Computer (CORDIC) designs with an additional area overhead. The new algorithm also reduces the amount of twiddle elements to a minimum while also simplifying the address generating process. A novel approach makes integrating FFT processors on single chips much easier. This approach is demonstrated to be notably efficient in procedures such as SVD or matrix triangularization, in which the calculation of the rotation angle is necessary.

The performance of neuromorphic systems is primarily determined by the interplay between neurons and learning models. Achieving an optimal trade‐off between their computational accuracy and hardware implementation complexity represents a fundamental challenge in pursuing brain‐like neural network designs. This paper introduces a two‐stage pipelined design for spiking neural networks (SNNs) utilizing an adaptive coordinate rotation digital computer (CORDIC) algorithm. Our approach begins with leveraging the adaptive CORDIC method to efficiently approximate square‐term computations in the Izhikevich neuron model, as well as the exponential calculations involved in the spike timing‐dependent plasticity (STDP) algorithm. In addition, a low‐overhead hardware circuit was developed to record the timing of spike firing. FPGA‐based online learning is subsequently implemented on an adaptive CORDIC Izhikevich neuron network. Performance is assessed regarding resource utilization, power efficiency, operational frequency, and computational accuracy, and the results are benchmarked against the latest advancements in the field. This design utilizes 199 look‐up tables (LUTs) and 336 registers per neuron, achieving a remarkably low power consumption of 4.6 mW. It operates at a maximum frequency of 434.7 MHz, with an average computation latency of 74 ns for a single MPI (message passing interface). Additionally, the STDP mechanism attains a peak operating frequency of 287.2 MHz. These results confirm the precision of the adaptive CORDIC‐based SNN, highlighting its superior performance in high‐speed operation, energy efficiency, and minimal area. Owing to these characteristics, the proposed design is particularly well‐suited for resource‐constrained, latency‐sensitive applications such as edge computing, autonomous robotics, and real‐time sensor processing.

In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

This paper presents a modified implementation of QR decomposition for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) detection based on the Givens rotation method. The QR decomposition hardware is constructed using the coordinate rotation digital computer (CORDIC) algorithm operating with fewer gate counts and lower power consumption than do triangular systolic array (TSA) structures. Accurate signal transmission is essential to wireless communication systems. Thus, a more effective data detection algorithm and precise channel estimation method play vital roles in MIMO systems. Implementing data detection with QR decomposition helps reduce the complexity of MIMO-OFDM detection. Implementation results reveal that the proposed recursive QR decomposition (RQRD) architecture has lower clock latency than do TSA structures, and has a smaller hardware area than do Gram–Schmidt structures.

Aiming at providing an efficient hardware architecture for generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems, in this paper a COordinate Rotation DIgital Computer (CORDIC) -based symbol detector is proposed. In the proposed detector, several CORDIC-based Givens rotation modules are conducted in parallel for the transmit antenna combinations (TACs) to facilitate QR-decomposition. After that, the proposed detector uses adders, shifters, and backward substitution mechanisms to currently estimate symbols for the corresponding TAC. At last, the estimated symbols and corresponding TAC index with the smallest distance measurement are chosen as the final solution. In particular, to achieve efficient hardware implementation, the architecture of the proposed detector has several features, including multiplication-free ranking mechanism, parallel CORDIC-based architectures, and shorter-bit-length multipliers. In addition, the overall architecture is pipelined to speed up the processing of the hardware. At last, simulation results reveal the proposed detector performs near to the optimal maximum likelihood (ML), but uses lower computational complexity. Additionally, the VLSI implementation results under the TSMC 90-nm CMOS technology show that the proposed hardware architecture requires 266K gates (KGEs), provides detection throughput 2.008 Gbps, works with pre-processing latency of 47 clock cycles, and has the hardware efficiency 7.54 (Mbps/KGEs) while operating at frequency 200.8 MHz. Moreover, implementation comparisons show the proposed architecture provides high throughput rate as well as hardware efficiency, and works with low pre-processing latency.

In response to the limitations of insufficient reconfigurability and excessive hardware resource overhead associated with traditional FFT circuits in multi-standard signal processing scenarios, this paper proposes a reconfigurable mixedradix FFT circuit design grounded in the CORDIC (Coordinate Rotation Digital Computer) algorithm. This design employs a hybrid basis $(2 / 3 / 4 / 5)$ decomposition structure, enabling the reconfigurable computation of FFTs with varying point counts through the dynamic configuration of computational units. An enhanced CORDIC algorithm is implemented in the rotation factor generation module, where an optimized set of rotation angles is utilized. This method effectively reduces hardware resource consumption and latency while ensuring computational accuracy. Simulation and experimental results conducted on an FPGA platform demonstrate that the design achieves a computational signal-to-noise ratio (SNR) of at least 60 dB, thereby meeting the precision requirements of most communication systems. When compared to similar FFT circuits, this design significantly decreases hardware resource utilization while maintaining comparable computational speed, resulting in an approximate power savings of $\mathbf{4 4\%}$. Keywords-Mixed-Radix FFT CORDIC Reconfigurable

This paper proposes the practical implementation of a DOA estimation system, using an FPGA (field programmable gate array), that is a key technique in the realization of the DOA-based adaptive array antenna for cellular wireless base-stations. It incorporates the spectral unitary MUSIC (multiple signal classification) algorithm, which is one of the representative super resolution DOA estimation techniques. This paper describes the DSP design and real hardware implementation of the unitary MUSIC algorithm. This system achieves a high performance in the eigenvalue decomposition (EVD) and MUSIC angular spectra computation with a cyclic Jacobi processor based on CORDIC (coordinate rotation digital computer) and spatial DFT (discrete Fourier transform), respectively. All DSP functions are computed by only fixed-point operation with finite bit-length to meet the requirements of fast processing and low power consumption due to the simplified and optimized architecture.

Carrier Interferometry orthogonal frequency division multiple access (CI-OFDMA) is an attractive choice for next-generation wireless communication and is considered as an alternative to OFDM with low peak-to-average-power-ratio (PAPR) and inter-carrier-symbol interference (ISI). The implementation of the real-time multicarrier communication system is restricted by the huge hardware cost and the complexity associated with a large number of computations. In this paper, a low-complexity real-time co-ordinate rotational digital computer (CORDIC)-based very-large scale integration (VLSI) architecture is proposed for CI-OFDMA system. To date, there is no field programmable gate array (FPGA) prototype that is addressed for the CORDIC-based real-time CI-OFDMA wireless system. In this context, we have proposed a new hardware-efficient and flexible CORDIC-based CI-OFDMA architecture. The novelty of this proposed architecture is its capability of changing the number of orthogonal subcarriers and user symbols upto the maximum 32K for the 16-bit word size architecture that is suitable for most of the current and upcoming wireless standards. The architecture is prototyped using commercially available FPGA device XC3S500E-5FG320. The implementation and experimental results of this proposed scheme are highlighted and validated with the result obtained by MATLAB simulation.