CORDIC Architectures: A Survey

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation.

In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (COordinate Rotation DIgital Computer) processor. In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes - one using adders in all the stages and another using multiplexers in the second and third stages. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.

CORDIC (COordinate Rotation Digital Computer) is an iterative algorithm for the calculation of the rotation of a two-dimensional vector, in linear, circular or hyperbolic coordinate systems, using only add and shift operations. This paper presents a novel algorithm and architecture for the rotation-mode in circular and hyperbolic coordinate systems in which the directions of all micro-rotations are pre-computed while maintaining a constant scale factor. Thus, an examination of the sign of the angle after each iteration is no longer required. By using a redundant adder, the critical path (without scaling and conversion) of the entire CORDIC architecture only requires (1.5n+2) full-adders (n corresponds to the word-length of the inputs) for rotation mode. This is a speed improvement of about 20% compared to the previously fastest reported rotation mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel feature of independence of the iterations i and i-1 in the CORDIC rotation. Optional pipelining can lead for example in the rotation mode to an on-line delay of three clock cycles including scaling and conversion, where every clock cycle corresponds to a delay of twelve full-adders.

Rotation is a basic operation for image processing, and the complexity of its computation is considered as the key problem of the implementation of real-time visual system. This paper proposes a novel architecture based on modified compensated CORDIC and bilinear interpolation algorithms in a recursive and folded way. The proposed modified compensated CORDIC algorithm compensates the scale factor in parallel with angle rotations, expands the convergence range to entire 2/spl pi/ and avoids pre- and post- rotations. The detailed architecture for image rotation is modeled by Verilog and implemented in Xilinx FPGA. Experiment results show that the proposed CORDIC algorithm has the lowest computational complexity and the architecture for real-time image rotation has lower hardware cost and power consumption.

The COordinate Rotation DIgital Computer (CORDIC) algorithm is a famous technique for realizing complex arithmetic functions using simple shift-add operations. This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for high performance hyperbolic computations. We target algorithm level improvements to achieve low area and power-delay product on FPGA. Instead of complex search algorithms, we use the most significant one bit detection technique for micro-rotation sequence identification, which helps in significantly reducing the number of pipelining stages. The proposed technique uses mathematical identities to extend the range of convergence. The eight-staged pipelined architecture implementation requires a ROM in the preprocessing unit for storing the initial coordinate values, while the ROM for storing the elementary angles is eliminated. The FPGA implementation of the proposed processor requires 46.35% less gates and has 31.81% less delay when compared with Xilinx Core IP-CORDIC v3.0. Moreover, on an average it consumes 75.96% less power when compared with Xilinx CORDIC v3.0. Hence, the proposed technique provides an area–power-delay efficient VLSI implementation for calculating hyperbolic functions and exponents. The detailed algorithm design, along with FPGA implementation and area and time complexities, is presented in this paper.

In this paper, we propose a CoOrdinate Rotation DIgital Computer (CORDIC) like processor for computing absolute magnitude of a vector and its corresponding phase angle. It does not require the scale factor compensation step and addition/subtraction operation along the z datapath, has a convergence range over the entire coordinate space and shows similar error characteristics as that of the conventional CORDIC. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications.

Neuromorphic hardware facilitates the fast and energy-efficient implementation of neural network-based artificial intelligence, making it particularly effective for addressing brain-inspired robotic challenges. The advancement of neuromorphic algorithms can continue to evolve in accordance with the principles of neural computing and the architectures of neural networks that draw inspiration from biological neural systems. In this perspective, we proposed a modified Izhikevich model that imitates the biological behaviors of the original neuron model using the Coordinate Rotation Digital Computer (CORDIC) algorithm. By employing adder and shifter operations to remove multipliers, the proposed method presents an effective digital hardware implementation of the Izhikevich model. The CORDIC-based Izhikevich model can accurately replicate the biological behaviors of the original model, according to error analysis and dynamic evaluations. Furthermore, the major goal of this work is to identify stable equilibrium points, chaotic regimes, and transitions between various dynamical states by investigating the dynamic behaviors of the proposed Izhikevich model under varying parameters. For this reason, the transitions from periodic to chaotic behavior are defined by applying numerical analyses, which include bifurcation diagrams and the maximum Lyapunov exponent. The potential for hardware implementation with high speed is the proposed model’s superiority over the original model, while it has a high compatibility level. In order to verify the effectiveness of the suggested hardware in comparison to previous studies, four cost functions are introduced based on operation frequency, power, and errors. Applying this method to the Spartan6 board can increase the speed of the proposed model by approximately 3.18 times compared to the original model. Therefore, the suggested hardware, whose features include low error rates, acceptable power consumption, and frequency capabilities, exhibits efficiency and impact in a variety of applications, such as modeling learning processes in the nervous system that are based on nonlinear and chaotic behaviors.

Synchro is a kind of angular measuring devices with high reliability widely used in avigation, spaceflight, military affairs and other fields. It aims to test positions, displacements and other angular information. CORDIC algorithm and its pipeline architecture were utilized by correcting the compensating factor based on FPGA. During the angular solution, we proposed a new method for angle mapping to accomplish the high speed solution to arctangent function. Mapping the angle divided into eight areas into one area ranged from 0 to 45deg uniformly. Hardware resources were saved as well. Programme was written by VHDL and proved true by implementing on the FPGA chip. In addition, the accuracy is high with the maximum absolute error of les 0.01deg. High speed and real time angular solution realized accurately so as to enhance accuracy of testing placements and positions system with low cost, high speed and high accuracy comes true.

In this paper, an improved fixed-point hardware design of QR decomposition, specifically optimized for Xilinx FPGAs is introduced. A Givens Rotation algorithm is implemented by using a folded systolic array and the CORDIC algorithm, making this very suitable for high-speed FPGAs or ASIC designs. We improve the internal cell structure so that the system can run at 246MHz with nearly 24M updates per second throughout on a Virtex5 FPGA. The matrix size can be easily scaled up.

This paper describes a new parallel micro cordic processor architecture most suitable for low power applications. In the proposed architecture parallel micro cordic algorithm was realized for the real time antenna array applications. Implementing this algorithm in the proposed architecturally modified micro cordic processor has the advantage of replacing the multiplication operations with shifting and adding logic and arithmetic operations. Thus it has less utilization of memory. A 2×2 Microsrtip patch phased array antenna was designed for transmission purpose. This low power micro cordic processor was interfaced to the Microsrtip patch phased array antenna. By using the proposed architecturally modified micro cordic processor the coordinate values were calculated for angular rotation of the Microsrtip patch array type antenna at a reference angle of 30 radians and the simulated results were studied. The micro cordic processor executions were verified using Xilinx and modelsim software. The information from micro cordic architecture was fed to the designed antenna for the angular rotations and results were evaluated at a reference angle of 30 radians. The VSWR, gain and return loss of the Microsrtip patch phased array antenna for the taken reference angle 30 radian were 2.8839, 1.9469dB and −28.5dB respectively.

This paper uses FPGA to design and implement CORDIC algorithm. Defining 16-bit data to complement switch, then it can calculate the sinusoidal value, cosine value and tangent value for any angle by CORDIC coordinate rotation algorithm, and gets the results close to the exact data through multiple iterations. The design is completed in QuartusII integrated development environment, and the RTL code simulation test is carried out on ModelSim. The angle value of each quadrant can be calculated effectively by using external control circuit and LCD screen. The simulation results and demonstration results verify the authenticity and validity of the CORDIC algorithm in this design.

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.