A new resource constrained asynchronous scheduling method through transformation of dataflow graphs

Division operation is very important in the computer system. Nowadays people use a hardware module─divider to implement the division algorithm. Conventionally synchronous techniques are applied to implement the divider. The synchronous systems always need system clock signals to trigger the system. However, the system clock of the synchronous system may cause some problems, such as clock skew, dynamic power consumption, ..., etc. Compared to synchronous systems, asynchronous circuits do not need system clock signals and thus the asynchronous system does not have the shortcomings mentioned above. Here we will propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is of simplicity and is very easy for the VLSI implementation. By this asynchronous architecture, we use TSMC’s 0.6um SPDM process to design a 32-b/32-b radix-2 non-restoring divider and the spice simulation proves it works. The HSPICE simulation shows that it can finish a 32-b/32-b division in between 3.7ns to 160.2ns.

Synchronous digital systems have been presenting serious problems of implementation in DSM (deep sub-micron) VLSI technology, for which the asynchronous paradigm has become an interesting alternative. Unfortunately, the topic of synthesis of asynchronous digital systems has been ignored or presents only a few numbers of teaching classes in most courses in electrical engineering, due the difficulty of different styles of asynchronous design, what requires many hours of classroom teaching. In this paper we propose a methodology for synthesis of asynchronous systems that requires just few hours of classroom teaching, being interesting to be incorporated in the subject of logic design. Starting from the RTL (Register Transfer Level) description of synchronous systems, the proposed method synthesizes the asynchronous system in the “decomposition” style, which is defined by XBM_AFSM (extended burst-mode asynchronous finite state machine) + datapath synchronous. A simple procedure is used to convert the specification of SFSM to the XBM specification, which describes the XBM_AFSM. Through a case study, it is shown the simplicity of the methodology, resulting in high-performance circuits.

Optical CDMA systems have been investigated widely to apply for high speed LAN, because they allow multiple users to access the network simultaneously. For optical CDMA systems, both asynchronous and synchronous systems have been studied. With synchronous CDMA, the available number of signature codes is larger than that of asynchronous CDMA systems. For a given value of bit error rate, synchronous CDMA systems can accommodate more simultaneous users than asynchronous CDMA systems. Furthermore, synchronous CDMA can be efficiently used in conjunction with TDMA and WDMA on multimedia communication networks.This chapter discusses sequences, modulations, system architectures used in optical synchronous CDMA systems and their performance.

Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchronous/synchronous interfaces.

Steady-state visual evoked potential (SSVEP)-based brain-computer Interface (BCI) has demonstrated the potential to manage multi-command targets to achieve high-speed communication. Recent studies on multi-class SSVEP-based BCI have focused on synchronous systems, which rely on predefined time and task indicators; thus, these systems that use passive approaches may be less suitable for practical applications. Asynchronous systems recognize the user's intention (whether or not the user is willing to use systems) from brain activity; then, after recognizing the user's willingness, they begin to operate by switching swiftly for real-time control. Consequently, various methodologies have been proposed to capture the user's intention. However, in-depth investigation of recognition methods in asynchronous BCI system is lacking. Thus, in this work, three recognition methods (power spectral density analysis, canonical correlation analysis (CCA), and support vector machine (SVM)) used widely in asynchronous SSVEP BCI systems were explored to compare their performance. Further, we categorized asynchronous systems into two approaches (1-stage and 2-stage) based upon the recognition process's design, and compared their performance. To do so, a 40-class SSVEP dataset collected from 40 subjects was introduced. Finally, we found that the CCA-based method in the 2-stage approach demonstrated statistically significantly higher performance with a sensitivity of 97.62±02.06%, specificity of 76.50±23.50%, and accuracy of 75.59±10.09%. Thus, it is expected that the 2-stage approach together with CCA-based recognition and FB-CCA classification have good potential to be implemented in practical asynchronous SSVEP BCI systems.

We propose the random Manchester codes (RMC) to improve the bit error probability (BEP) performance in both synchronous and asynchronous fiber-optic code-division multiple-access (CDMA) systems. The spreading sequences used in the synchronous and asynchronous systems are modified prime sequence codes and optical orthogonal codes (OOCs), respectively. Thermal noise, shot noise, and avalanche photodiode (APD) bulk and surface leakage currents are taken into consideration in the BEP analyzes. The results show that the proposed systems can support a larger number of simultaneous users than other systems with similar system complexity under the same bit-error probability constraint.

This issue presents five regular papers and two short papers exposing recent advances in the design of asynchronous systems. Most of the contributions were originally presented at the 14th IEEE International Symposium on Asynchronous Circuits and Systems, held in Newcastle upon Tyne, U.K., in April 2008.

After analyzing the requirement of large-scale equipment installation, both the functions and the faults of asynchronous collaborative design system and synchronous collaborative design system were discussed. And then, a combined collaborative design platform, which combined the product data management system with the synchronous collaborative design system, was proposed. A framework for the combined collaborative design platform was put forward. The product data management system and the synchronous collaborative design system were discussed in detail. And then, the strategies for sharing and exchanging of product data and information were presented. Operation steps of the combined collaborative platform were described in detail. Finally presented was a case study that using the combined collaborative design platform in electric dust collector installation.

We shall not restate all that was said at the beginning of the last chapter. It is sufficient to recall that assignment represents an important step in the realization of a sequential machine. However, it seems a good idea to insist on the fundamental difference between the problem for synchronous and asynchronous systems.

The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

In this paper, the performance of a binary phase shift keyed random\ntime-hopping impulse radio system with pulse-based polarity randomization is\nanalyzed. Transmission over frequency-selective channels is considered and the\neffects of inter-frame interference and multiple access interference on the\nperformance of a generic Rake receiver are investigated for both synchronous\nand asynchronous systems. Closed form (approximate) expressions for the\nprobability of error that are valid for various Rake combining schemes are\nderived. The asynchronous system is modelled as a chip-synchronous system with\nuniformly distributed timing jitter for the transmitted pulses of interfering\nusers. This model allows the analytical technique developed for the synchronous\ncase to be extended to the asynchronous case. An approximate closed-form\nexpression for the probability of bit error, expressed in terms of the\nautocorrelation function of the transmitted pulse, is derived for the\nasynchronous case. Then, transmission over an additive white Gaussian noise\nchannel is studied as a special case, and the effects of multiple-access\ninterference is investigated for both synchronous and asynchronous systems. The\nanalysis shows that the chip-synchronous assumption can result in\nover-estimating the error probability, and the degree of over-estimation mainly\ndepends on the autocorrelation function of the ultra-wideband pulse and the\nsignal-to-interference-plus-noise-ratio of the system. Simulations studies\nsupport the approximate analysis.\n

Lamport’s Happened-before relation is fundamental to coordinating actions in asynchronous systems. Its role is less dominant in synchronous systems, in which bounds are available on transmission times over channels. This paper initiates a study of the role that time bounds play in synchronous systems by focusing on two classes of problems: Ordered Response, in which a triggering event must be followed by a sequence of events (“responses”) performed in a prescribed temporal order, and Simultaneous Response, in which the responses must be performed simultaneously. In both cases, information about the triggering event must flow from its site of origin to the responding sites, and the responses must be timed as specified. A generalization of happened- before called Syncausality, is defined. A pattern of communication consisting of a syncausal chain coupled with an appropriate set of time bound guarantees gives rise to a communication structure called a centipede. Centipedes are a nontrivial generalization of message chains, and their existence is shown to be necessary in every execution of every protocol that solves ordered response. A variation on centipedes called centibrooms are shown to play an analogous role for Simultaneous Response: Every execution of a protocol for Simultaneous Response must contain a centibroom.Keywordssynchronous message passingbounded communicationordered responsesimultaneous responsecausalitysyncausalityknowledgecommon knowledgelevels of knowledgeknowledge and time

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

Improving the Responsiveness of the Synchronous Messaging System in FTT-CAN

We consider the consensus problem in a partially synchronous system with Byzantine faults. In a distributed system of n processes, where each process has an initial value, Byzantine consensus is the problem of agreeing on a common value, even though some of the processes may fail in arbitrary, even malicious, ways. It is shown in [11] that — in a synchronous system — 3t + 1 processes are needed to solve the Byzantine consensus problem without signatures, where t is the maximum number of Byzantine processes. In an asynchronous system, Fischer, Lynch and Peterson [7] proved that no deterministic asynchronous consensus protocol can tolerate even a single non-Byzantine (= crash) failure. The problem can however be solved using randomization for benign and Byzantine faults. For Byzantine faults, Ben-Or [2] and Rabin [12] showed that this requires 5t + 1 processes. Later, Bracha [3] increased the resiliency of the randomized algorithm to 3t + 1.