Guest Editorial: Special Section on Asynchronous Circuits and Systems

Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchronous/synchronous interfaces.

Division operation is very important in the computer system. Nowadays people use a hardware module─divider to implement the division algorithm. Conventionally synchronous techniques are applied to implement the divider. The synchronous systems always need system clock signals to trigger the system. However, the system clock of the synchronous system may cause some problems, such as clock skew, dynamic power consumption, ..., etc. Compared to synchronous systems, asynchronous circuits do not need system clock signals and thus the asynchronous system does not have the shortcomings mentioned above. Here we will propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is of simplicity and is very easy for the VLSI implementation. By this asynchronous architecture, we use TSMC’s 0.6um SPDM process to design a 32-b/32-b radix-2 non-restoring divider and the spice simulation proves it works. The HSPICE simulation shows that it can finish a 32-b/32-b division in between 3.7ns to 160.2ns.

Asynchronous designs employ handshaking to perform communication and data transfer between elements in a system. This method was employed in computer architecture as early as the 1950's. Much has changed since those early days. Rather than design with vacuum tubes and discreet devices, current technology enables designs that can have billions of transistors with 32 nm feature sizes. Asynchronous design technology has likewise advanced. The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum covering recent technological advances in this area of research. This annual conference brings together researchers and industry experts from around the world to discuss a broad range of topics covering all aspects of asynchronous design and related emerging technologies.

This paper describes a globally asynchronous, locally dynamic system (GALDS) design paradigm. In a GALDS design, many synchronous blocks are inter-connected using dedicated asynchronous links. Each synchronous block is associated with a local clock generator and features dynamic frequency scaling in order to utilize the least possible power for the required performance to be achieved. Two different asynchronous structures are explored in this paper and they each feature high throughput, modular design and high tolerance to metastability errors that occur when communicating between clock domains. These structures utilize a 4-phase dual track asynchronous control circuit to control either a single direction FIFO with data traveling uniquely in one direction or a bidirectional FIFO that is capable of transmitting data simultaneously in both directions by precisely controlling when data has access to a common, shared datapath. These structures have been created in TSMC's CMOSP18 technology.

After analyzing the requirement of large-scale equipment installation, both the functions and the faults of asynchronous collaborative design system and synchronous collaborative design system were discussed. And then, a combined collaborative design platform, which combined the product data management system with the synchronous collaborative design system, was proposed. A framework for the combined collaborative design platform was put forward. The product data management system and the synchronous collaborative design system were discussed in detail. And then, the strategies for sharing and exchanging of product data and information were presented. Operation steps of the combined collaborative platform were described in detail. Finally presented was a case study that using the combined collaborative design platform in electric dust collector installation.

Synchronization is a vital process for mobile system operations. Yet, in practice, it is not always convenient to derive timing information from stable clock sources. We discuss the inter-base-station timing mechanisms evolved for the two third-generation system proposals CDMA2000 and WCDMA. From the discussion, we review the merits and limitations of both approaches and highlight an alternative method based on self-synchronization. By using self-synchronization in third-generation systems, we can avoid the need for compromising performance through the adoption of asynchronous radio system design.

A mechanism for controlling the emitted traffic to asynchronous transfer mode (ATM) network, system design and implementation architectures are introduced. Specifically, the effective rate of a stream, defined under certain multiplexing conditions and quality‐of‐service specifications, is enforced to desired values by controlling the cell emission rate of the generated bursts. The traffic shaping mechanism is closely associated to an ATM transmitter, which is mainly responsible for ATM cell assembly and header error control. The mechanism has been designed to support data communication services. The whole system has been implemented as a VLSI circuit. Copyright © 2002 John Wiley & Sons, Ltd.

The introduction of HDLs (hardware description languages) have made a significant contribution to VLSI circuit design. While these languages are well suited to describe circuits in great detail, they are found wanting when attempting formal verification of circuits. One of the drawbacks lies in the lack of formal models of semantics. VHDL, with a wide variety of tools available to carry out circuit simulations, is the de facto standard used in VLSI design. On the other hand, the family of synchronous languages has been well studied for the design and synthesis of provably correct reactive systems. Thus, it behooves one to explore the possibility of interfacing languages such as VHDL with synchronous programming languages to handle higher levels of abstraction in circuit design with assured correctness. In this paper, we show how the paradigm of multiclock ESTEREL provides a framework for the design of multi-clocked systems and asynchronous systems. Multiclock ESTEREL can be used for modeling in conjunction with VHDL to enable formal verification of circuit behavior. We also show that multiclock ESTEREL captures the VHDL timing model succinctly. Multiclock ESTEREL can be used either in conjunction with VHDL or as a replacement depending on the requirements at hand. When used in conjunction, Multiclock ESTEREL can be used to describe circuits at higher levels of abstraction while VHDL can be used to describe the signal propagation characteristics.

Development of asynchronous data processing system is usually based on dedicated asynchronous elements. Advanced generalpurpose microprocessors have a set of features facilitating development of asynchronous data processing system. Such a system is designed for non-stationary signals using non-conventional digital signal processing methods. Implementation of the principles of the data level-crossing sampling, switching system to power reduction modes and asynchronous interaction between system units is determining asynchronous nature of the system. Paper represents architecture of the system implemented on Philips P89PLC936 microcontroller using a principle of the level-crossing sampling. The system is able to process input signal with maximum frequency fmax = 2kHz using sampling level number N = 7. Ill. 3, bibl. 10 (in English, summaries in English, Russian and Lithuanian).

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fibre delay line (FDL) buffer. In this study, the authors propose to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e. the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

Synchronous digital systems have been presenting serious problems of implementation in DSM (deep sub-micron) VLSI technology, for which the asynchronous paradigm has become an interesting alternative. Unfortunately, the topic of synthesis of asynchronous digital systems has been ignored or presents only a few numbers of teaching classes in most courses in electrical engineering, due the difficulty of different styles of asynchronous design, what requires many hours of classroom teaching. In this paper we propose a methodology for synthesis of asynchronous systems that requires just few hours of classroom teaching, being interesting to be incorporated in the subject of logic design. Starting from the RTL (Register Transfer Level) description of synchronous systems, the proposed method synthesizes the asynchronous system in the “decomposition” style, which is defined by XBM_AFSM (extended burst-mode asynchronous finite state machine) + datapath synchronous. A simple procedure is used to convert the specification of SFSM to the XBM specification, which describes the XBM_AFSM. Through a case study, it is shown the simplicity of the methodology, resulting in high-performance circuits.

This paper presents an extension of the basic concepts established by Robert McNaughton and David Muller in the field of asynchronous feedback networks. The ideas developed herein are the results of adapting common logical functions in a manner that simplifies the overall design of asynchronous systems. The prime objecttive is to overcome a weakness common to both of the aforementioned concepts, that of a network requiring storage for each input to it. In addition, a method is proposed to eliminate Muller's requirement of maintaining a spacer between the binary bits that a system processes. Finally, consideration is given to the idea of developing a three level logic feedback network which permits single line representation of data rather than the accepted two line approach.

Due to the increasing demand for mobile devices, the search for ultra-low-power projects is becoming a priority. One technique that allows a strong reduction of circuits dissipated power is the sub-threshold voltage operation, but it leads to some drawbacks. The QDI (Quasi Delay Insensitive) asynchronous circuits class show to be an interesting solution to these problems, when presented in synchronous circuits and in CMOS-UDSM (Ultra Deep Sub-Micron) technology. Asynchronous finite state machines (AFSMs) are important components in an asynchronous system. This paper proposes a new architecture for QDI_AFSMs. These machines are described in the extended burst-mode (XBM) specification and synthesized in a very simple way. The QDI_XBM_AFSMs are implemented in the dual-rail style, using NCL (NULL Convention Logic) gates. The resulting AFSMs are QDI, so they can operate with sub-threshold voltage. The architecture is presented through the case study and the obtained QDI_XBM_AFSM shows interesting results, when compared with two QDI controller of the literature, which are based on basic gates and C element.

With the increase of popularity in an asynchronous system design style, the request for asynchronous high-level synthesis tools is increasing continuously. In this paper, we suggest a new resource constrained asynchronous scheduling method which is performed through transformation of a dataflow graph (DFG). Experimental results show that the suggested scheduling method can produce a correct and efficient schedule from an initial DFG and the resulting schedule leads to a faster and more flexible asynchronous system compared to a corresponding synchronous system.

The asynchronous circuits from digital electronics are modeled by Boolean asynchronous dynamical systems, consisting in functions Φ : {0, 1}n → {0, 1}n that iterate their coordinates Φ1, ..., Φn independently on each other. The purpose of this work is to give a Lyapunov-Lagrange type theorem that characterizes the invariance of the sets A ⊂ {0, 1}n in the case of these systems.