A NEW TOPOLOGY ORIENTED METHOD FOR SYMBOLIC ANALYSIS OF ELECTRONIC CIRCUITS

SummaryKnowing the Network Function (NF) pertaining to a certain input–output couple individuated inside a linear electrical network (LEN) is crucial, as it provides a synthetic and effective description of the input–output relationship and allows one to derive several key features of the subject system as well as to devise proper strategies to modify them.From a mathematical point of view, an NF may be expressed as the product of a real number, called the gain constant (GC), by a real rational function of the complex variables, whose numerator and denominator are called the zero polynomial (ZP) and the characteristic polynomial (CP), respectively, and may be obtained by calculating the determinants of proper matrices. However, when a design‐oriented symbolic hand analysis is needed, calculating the said polynomials in this manner may turn out to be tediously cumbersome; and above all, such a route may fail to illuminate the way that their coefficients depend on the circuit elements. The same may be said of numerical computer methods, which are suited to providing a global description of the NF in the frequency domain rather than analytical expressions of its coefficients. In this paper, a method is proposed that permits one to obtain the ZP without calculating any determinants. With respect to other methods that achieve the same goal, the present one does not require prior calculation of the CP or a nullator‐norator pair (NNP) to be compulsorily inserted in the subject circuit. Instead, it is based on applying the Andreani‐Mattisson extension (AME) of the Cochrun–Grabel algorithm (CGA) for the calculation of the CP to a circuit obtained from the assigned one by inserting in the latter a proper dependent source. The nature of such new circuit allows the worker to employ the classical tools of LEN theory so as to make the analysis as simple as possible and often performable by straightforward inspection, without the need for possibly involved equilibrium equations. Moreover, it is shown how the same technique can be applied to a properly modified version of the original network in order to calculate the CP as well. In this case (not compulsorily but if judged convenient for simplifying the calculations), a NNP may be employed in conjunction with the dependent source. The proposed method once again allows one to exploit the classic tools of LEN theory so as to considerably, if not drastically, simplify the analysis associated with the direct application of the AME to the original network. Finally, the calculation of the GC (that completes the knowledge of the whole NF under study) as well as circuit degeneracy are discussed and practical examples of application of the proposed techniques are given. Copyright © 2013 John Wiley & Sons, Ltd.

Introduction The design of a mobile network architecture aims at defining network elements (e.g. Base Stations [BSs], switches, routers, user devices) and their interaction in order to ensure a consistent system operation. This chapter discusses basic considerations and provides an overview of current research activities. Network architecture can be considered from different angles that are needed in order to fulfill objectives like integration of technical components into an overall system, proper interworking of multi-vendor equipment and efficient design of physical networks from cost and performance point of view. As 5G systems have to integrate a plethora of partly contradicting requirements, enablers such as Network Function Virtualization (NFV) and Software Defined Networking (SDN) are to be applied in order to provide the needed flexibility of future networks, especially for the core network. Applying these tools may require a rethinking of some traditional aspects of network architecture design. This chapter will give the reader an impression of the most important topics influencing architecture design of future networks. NFV and SDN Today's operator networks include a large and increasing variety of hardware appliances. Launching new services often requires integration of complex hardware dedicated to the service including costly procedure design and is associated with lengthy time to market. On the other hand, hardware life cycles become shorter as technology and service innovation accelerates. At the end of 2012, network operators have started an initiative on NFV [1]. NFV aims at consolidating the variety of network equipment onto industry-standard high-volume servers. These servers can be located at the different network nodes as well as end-user premises. In this context, NFV relies upon but differs from traditional server virtualization. Unlike server virtualization, Virtualized Network Functions (VNF) may consist of one or more virtual machines running different software and processes in order to replace custom hardware appliances (Figure 3.1). As a rule, multiple VNFs are to be used in sequence in order to provide meaningful services to the customer. NFV requires an orchestration framework that enables proper instantiation, monitoring and operation of VNFs and Network Functions (NFs) (e.g. modulation, coding, multiple access, ciphering, etc.).

By using Network Function Virtualization (NFV), several kinds of network functions can be provided in commercial off-the-shelf (COTS) servers. Such network function is called Virtual Network Function (VNF). In terms of the utilization of VNFs, an emerging technology called service chaining enables network operators to provide network services dynamically and flexibly. Here, the number of VNF instances should be managed dynamically according to the amount of traffic. In this paper, we propose a dynamic management of VNF instances with Model Predictive Control (MPC) for multiple service chains. In the proposed method, the number of VNF instances is changed dynamically according to the predicted amount of traffic. We evaluate the performance of the proposed method and threshold method with simulation. In numerical examples, it is shown that the proposed method can avoid data loss with a small number of VNF instances.

This article develops a new method of data-driven modeling for a class of multiple-transmitter single-receiver wireless power transfer (WPT) systems. A continuous-time multiple-input single-output (MISO) model with pure time delays is used to characterize the input–output behavior of the system, where the transfer functions associated with each input channel are not constrained to have the same denominator. Moreover, the time delays are allowed to be a fraction of the sampling interval in order to account for the delay effects that stem from circuit components and wireless communication, which are, by nature, often a fraction of the sampling interval. An optimal refined instrumental variable method is proposed to estimate the parameters and time delays of the MISO model based on sampled input–output data. In contrast to the conventional circuit-theory-based modeling methods that rely on circuit parameters and result in models which are often complex, the proposed data-based method yields parsimonious models, whose parameters are directly estimated from input–output data. Due to the easy availability of sampled data in control engineering applications, the proposed method is clearly more user-friendly, having a broad prospect for efficient operation of WPT systems, such as prediction, optimization, and control. Numerical and experimental results are presented to validate the effectiveness and merit of the proposed method.

The sensitivity of network functions of a circuit containing an ideal voltage amplifier to the amplification-factor variation of this element is expressed with the help of various auxiliary network functions determined in the original circuit or in the circuit from which the ideal voltage amplifier was removed. The procedure is suitable for practical sensitivity measurements.

The prominent feature of the degradation of metal oxide surge arrester is an obvious increase of the resistive current, especially its fundamental and third harmonic, so it is very important to measure the resistive current. In this paper, a new method for the measurement of the resistive current is presented. At first, the time-domain equations of the resistive current, the capacitive current and the total leakage current on the applied voltage are deduced based on the equivalent model of MOA. According to the observed data and the fitted data of the total leakage current, the least square is then used to obtain the circuit parameters of the equivalent model. By substituting these circuit parameters into the relevant time-domain equations, both the resistive current and the capacitive current are obtained. In addition, the influence of the circuit parameters, harmonic voltage and current noise on the proposed method is also studied. The simulation results show that the proposed method can extract the resistive current exactly when the applied voltage and the total leakage current are ideal. The circuit parameters, harmonic voltage and current noise have little effect on the proposed method. Moreover, the proposed method can not only obtain the resistive current and the capacitive current at the same time, but give the circuit parameters of MOA as well.

A new and efficient algorithm for topological formulation of network functions in symbolic form for a general linear (passive or active) network is presented. This algorithm, which is based on the concept of graph partitioning developed by Dunn and Chan, has all of the advantages of the existing topological formulas, such as overcoming the problem of sign evaluation and greatly reducing the number of term cancellations and the number of topological terms. In addition, and perhaps the most important, it presents a step-by-step procedure for formulating network functions that can readily be adapted for computer implementation. Finally, it is shown that the theoretical results developed herein are most suited for sensitivity analysis of linear active networks.

предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключевую роль, сравнивая опорное напряжение с выходным (или частью выходного) напряжением, и управляет проходным элементом для обеспечения этого равенства. Представлены описание электрических схем усилителей, основные электрические характеристики, результаты моделирования, указаны особенности разработки топологии интегральной схемы. ОУ разработаны на базе отечественного технологического процесса с проектными нормами 3 мкм. Разработка схемы и топологии проводилась в специализированной системе автоматизированного проектирования интегральных схем. Для моделирования схемы использовались сертифицированные математические модели полупроводниковых приборов. Разработанные топологии ОУ прошли верификацию, состоящую из проверки соблюдения проектных норм (Design rule check, DRC), восстановления электрической схемы из топологии и сравнения топологии с исходной схемой (Layout vs Schematic, LVS) the article proposes two IP blocks of operational amplifiers (op-amps) built on n-channel and p-channel differential pairs. Op-amps are universal blocks on the basis of which you can build many different electronic devices. Currently, op amps are widely used, both in the form of individual chips and as IP blocks as part of more complex integrated circuits. The developed IP blocks are intended for use in integrated circuits of linear voltage stabilizers as error amplifiers. In voltage regulators, the error amplifier plays a key role by comparing the reference voltage to the output (or part of the output voltage) voltage and drives the pass element to ensure this equality. The description of the electrical circuits of amplifiers, the main electrical characteristics, the results of modeling are presented, the features of the development of the integrated circuit topology are indicated. The op amps are developed on the basis of the domestic BiCMOS technological process with design standards of 3 µm. The development of the scheme and topology was carried out in a specialized system for automated design of integrated circuits. To model the circuit, certified mathematical models of semiconductor devices were used. The developed layouts of the op-amp have passed verification, consisting of checking compliance with design standards (Design rule check, DRC), restoring the electrical circuit from the layout and comparing the layout with the original circuit (Layout vs Schematic, LVS)

Network function virtualization (NFV) is a new networking paradigm based on decoupling network functions from dedicated hardware, so these network functions can be run as pieces of software on general-purpose computation servers, which are called virtual network functions. In addition to guarantee the service qualities provided by NFV networks comparable to those provided by traditional telecommunication networks, energy consumption becomes one of the challenges faced by NFV. This is due to a large number of general computation servers that consume a significant amount of energy. We address here the problem of how to provide an energy-aware service function chaining (SFC) embedding in NFV networks with a hierarchical resource allocation, where an SFC has a set of virtual network functions to be executed in a specific sequential order providing a specific network service. Assuming a dynamic traffic scenario, we introduce for this new problem an integer linear programming (ILP) and three polynomial heuristic algorithms for resource allocation. All three heuristic algorithms achieve energy savings by shutting down idle devices and balance the tradeoff between energy cost and SFC request acceptance ratio. Numerical results demonstrate the quality of the proposed heuristic algorithms in terms of acceptance ratio by comparing them with the ILP method and a method extended from an exiting algorithm despite the fact that they save energy.

ABSTRACTEarly‐born γ‐aminobutyric acid (GABA) neurons (EBGNs) are major components of the hippocampal circuit because at early postnatal stages they form a subpopulation of “hub cells” transiently supporting CA3 network synchronization (Picardo et al. [2011] Neuron 71:695–709). It is therefore essential to determine when these cells acquire the remarkable morphofunctional attributes supporting their network function and whether they develop into a specific subtype of interneuron into adulthood. Inducible genetic fate mapping conveniently allows for the labeling of EBGNs throughout their life. EBGNs were first analyzed during the perinatal week. We observed that EBGNs acquired mature characteristics at the time when the first synapse‐driven synchronous activities appeared in the form of giant depolarizing potentials. The fate of EBGNs was next analyzed in the adult hippocampus by using anatomical characterization. Adult EBGNs included a significant proportion of cells projecting selectively to the septum; in turn, EBGNs were targeted by septal and entorhinal inputs. In addition, most EBGNs were strongly targeted by cholinergic and monoaminergic terminals, suggesting significant subcortical innervation. Finally, we found that some EBGNs located in the septum or the entorhinal cortex also displayed a long‐range projection that we traced to the hippocampus. Therefore, this study shows that the maturation of the morphophysiological properties of EBGNs mirrors the evolution of early network dynamics, suggesting that both phenomena may be causally linked. We propose that a subpopulation of EBGNs forms into adulthood a scaffold of GABAergic projection neurons linking the hippocampus to distant structures. J. Comp. Neurol. 524:2440–2461, 2016. © 2016 Wiley Periodicals, Inc.

LINEAR CIRCUIT ANALYSIS. Fundamental Circuit Concepts. Network Laws and Theorems. Terminal and Port Representation. Signal Flow Graphs in Filter Analysis and Synthesis. Analysis in the Frequency Domain. Tableau and Modified Nodal Formulations. Frequency Domain Methods. Symbolic Analysis. Analysis in the Time Domain. State-Variable Techniques. FEEDBACK CIRCUITS. Feedback Amplifier Theory. Feedback Amplifier Configurations. General Feedback Theory. The Network Functions and Feedback. Measurement of Return Difference. Multiple-Loop Feedback Amplifiers. Index.

Promising recent research suggests that more cognitively demanding interviews improve deception detection accuracy. Would these cognitively demanding techniques work in the same way when discriminating between true and false future intentions? In Experiment 1 participants planned to complete a task, but instead were intercepted and interviewed about their intentions. Participants lied or told the truth, and were subjected to high (reverse order) or low (sequential order) cognitive load interviews. Third-party observers watched these interviews and indicated whether they thought the person was lying or telling the truth. Subjecting participants to a reverse compared to sequential interview increased the misidentification rate and the appearance of cognitive load in truth tellers. People lying about false intentions were not better identified. In Experiment 2, a second set of third-party observers rated behavioral cues. Consistent with Experiment 1, truth tellers, but not liars, exhibited more behaviors associated with lying and fewer behaviors associated with truth telling in the reverse than sequential interview. Together these results suggest that certain cognitively demanding interviews may be less useful when interviewing to detect false intentions. Explaining a true intention while under higher cognitive demand places truth tellers at risk of being misclassified. There may be such a thing as too much cognitive load induced by certain techniques

An improved symbolic analysis procedure to enhance the analytic efficiency of the reported symbolic nodal analysis is presented. Two techniques are adopted in the proposed method to reduce the order of the system of equations when performing symbolic analysis. The first one uses voltage signal sources directly to perform symbolic analysis without replacing them with their nullor equivalences. The second one uses the nullor, grounded mirror, and floating mirror elements to model the active devices that involve differential or multiple single-ended signals. Practical examples are given which demonstrate the feasibility of the proposed methods.

Proton Exchange Membrane Fuel Cell (PEMFC) which is an efficient renewable energy system has usage area in home and industrial applications. Since the generated voltage from PEMFC is low, the output voltage of it can be increased by using a boost converter. The boost converter fed by PEMFC can normally be controlled by the classical PI controller which parameters (K P , K i ) are constant and do not depend on the circuit parameters. Therefore, these coefficients are non-adaptive at variable load situations. In this study, an improved controller is obtained by regulating the PI controller according to Lyapunov stability theorem. Then, this improved Lyapunov based PI controller is proposed for PEMFC based boost converter. In the proposed method, K P and K i parameters vary adaptively depending on the circuit parameters. Thus, the system works more stable and settling time of system's output voltage signal decreased compared to classical PI controller. The proposed method has been successfully tested in Matlab/Simulink environment.

The paper demonstrates how electrical variables, when formulated as vector quaternions, can be manipulated. Circuit parameters can easily be obtained, for analytical purposes. Quaternions, which were discovered 170 years ago, are the basis for four dimensional vectors. Electrical variables fit into this realm, as some circuit variables are in quadrature with one another when viewed across different circuit components. The manipulation of the variables to obtain power, energy and impedance is shown to be simple and visual when vectors are looked at, in various planes of the four dimensional space. Other applications of quaternions and complex numbers in the general field of electrical engineering are also alluded to in the paper for completeness and in particular the famous and initial application of quaternions in electric field theory analysis by James Clerk Maxwell.