• Cite Icon2
  • https://doi.org/10.1109/t-ed.1982.21027Copy DOI Icon

A novel buried-drain DMOSFET structure

Show More
  • Abstract
  • Literature Map
  • References
  • Citations
  • Similar Papers
Abstract

A novel buried-drain MOSFET (BDMOS) structure is presented which utilizes a double-implanted source region to achieve short-channel lengths. The fabrication sequence of a six-mask silicon-gate process shows the highlights of this new technology. Strong emphasis has been given on using process and device simulation tools, in order to optimize device performance. Experimental results on fabricated devices with source-drain distances between 0.5 and 3 µm and active channel lengths of 0.25 µm show the inherent potential of this new structure.

Similar Papers
  • Conference Article

Investigation of the effect of the extension implant energy on deep submicron CMOS device performance

  • Sep 22, 1997
  • Stefan Kubicek +2
  • Research Article
  • Citations5

Vertical-Type a-Si:H Field-Effect Transistors

  • Jan 01, 1984
  • MRS Proceedings
  • Yasutaka Uchida +1
  • Research Article
  • Citations28

Flow channels/fiber impregnation studies for the process modeling/analysis of complex engineering structures manufactured by resin transfer molding

  • Oct 01, 1998
  • Polymer Composites
  • R V Mohan +3
  • Book Chapter
  • Citations4

Value-Added Products from Wastes Using Extremophiles in Biorefineries: Process Modeling, Simulation, and Optimization Tools

  • Jan 01, 2018
  • Elias Martinez-Hernandez +4
  • Research Article
  • Citations182

Two-dimensional surface dopant profiling in silicon using scanning Kelvin probe microscopy

  • Mar 01, 1995
  • Journal of Applied Physics
  • Albert K Henning +6
  • Book Chapter

Efficient Integration of Device and Circuit Simulation

  • Jan 01, 1989
  • P O'Sullivan +2
  • Book Chapter

IC Technology CAD Overview

  • Jan 01, 1994
  • P Lloyd
  • Conference Article
  • Citations2

Combining TCAD and advanced metrology techniques to support device integration towards N3

  • Jun 10, 2021
  • P Eyben +12
  • Conference Article

MOSFET process optimization and characteristics extraction

  • Jan 01, 2004
  • F Babarada +6
  • Research Article
  • Citations60

Computational model of mesoscopic structure of concrete for simulation of fracture processes

  • Jan 04, 2007
  • Computers & Structures
  • J.P.B Leite +2
  • Research Article
  • Citations45

Process design using two-dimensional process and device simulators

  • Feb 01, 1982
  • IEEE Transactions on Electron Devices
  • Daeje Chin +3
  • Research Article
  • Citations34

Direct patterning of silver electrodes with 2.4 μm channel length by piezoelectric inkjet printing

  • Oct 11, 2016
  • Journal of Colloid and Interface Science
  • Honglong Ning +12
  • Conference Article
  • Citations1

The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology

  • Jan 01, 1980
  • D Takacs +2
  • Research Article
  • Citations115

Integration of life cycle assessment software with tools for economic and sustainability analyses and process simulation for sustainable process design

  • Jan 22, 2014
  • Journal of Cleaner Production
  • Sawitree Kalakul +3
  • Research Article
  • Citations69

Mismatch Characterization of Submicron MOS Transistors

  • Feb 01, 1997
  • Analog Integrated Circuits and Signal Processing
  • J Bastos +3
Cactus Communications logo

Copyright 2026 Cactus Communications. All rights reserved.