Efficient Integration of Device and Circuit Simulation

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.

TCAD software needs equipment input settings and models to create the process environment for process and device simulation tools like TSUPREM4 and MEDICI. After optimisation the next step is the circuit simulation and design using software packages like SPICE. First using design of experiments-DOE and response surface modelling-RSM techniques we optimise the MOSFET characteristics and then we compare the transfer characteristics of n-type MOSFET, biased in the linear region, and obtained from package respectively TSUPREM4 and MEDICI with transfer characteristics from PSPICE. Using the PSPICE second level model for MOS transistor we obtain a good fit with MEDICI transfer characteristics.

This paper gives an overview of predictive Technology CAD tools for simulating and modeling the fabrication and electrical behavior of integrated circuits. Recent trends in the integration of process, device, and circuit simulation tools, and the current emergence of UNIX based computing environments of networked workstations make possible user-friendly, task-based CAD systems for technology optimization, characterization, and cell design.

Industry-standard TCAD software packages are widely used by semiconductor companies to optimise processes and devices in integrated circuits fabrication. After process and device simulation one can go ahead with circuit simulation using Spice. This paper focuses on the matching of these program packages in the area of parameter and characteristics extraction. We compared the transfer characteristics of n-type MOSFET, biased in the linear region, obtained from Synopsys package including TSUPREM4 and MEDICI with transfer characteristics from PSpice package.

The degradation of MOSFET device performance in time (aging), caused by hot-carrier injection (HCI) and negative/positive bias-temperature instability (N/PBTI), is increasingly more responsible for IC reliability failure in advanced process technology nodes. Device scaling, that has allowed increased performance of CMOS circuits, has also resulted in a magnification of such reliability issues. At the same time, device and circuit designers face increasingly stronger requirements to provide realistic estimates of product reliability as a function of circuit operation conditions. Accurate aging modeling and fast yet trustable reliability signoff have thus become mandatory in process development and circuit design. This paper presents an accurate and scalable compact device aging model that takes into account accurately the HCI and BTI mechanisms and is silicon proven for various processes down to 32/28nm. The model formulation on bias, geometry and temperature and, in particular, a unique methodology for modeling the AC partial-recovery effect of BTI, is analyzed in detail. The model has been embedded in an efficient MOSRA circuit simulation flow and has been used successfully for numerous takeouts and silicon debugging for 45nm and below.

In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.

Roentgenographic Examination of Dental Gold Alloys

Technical analysis of intellectual property (IP) is conducted for the purpose of legal protection and product development. A brief review of the process of IP analysis and associated terminology is...

In recent past, there has been massive research in the field of organic electronics. Many novel techniques are proposed for improving the device and circuit performance. The use of the dual gate organic thin film transistor (DG-OTFT) provides one such technique to enhance the overall performance of organic devices and circuits. The DG-OTFT not only boosts the performance of the device and circuit but also makes them robust. This research paper analyzes the in-depth behavior of the DG-OTFT for top gate, bottom gate and dual gate modes of operation in terms of drive current, mobility, threshold voltage, sub-threshold slope and current on-off ratio. The observed results show higher drive current in the dual gate mode due to formation of two channels resulting in higher carrier injection. The electrical characteristics and performance parameters of DG-OTFT based on PDPP-TNT as organic semiconductor are evaluated and validated with the reported experimental results. The simulation results are in close agreement with experimental data. Consequently, the static and dynamic behavior of organic SR latch based on all p-type DG-OTFT is investigated using organic module of Atlas 2-D numerical device simulator.

Combined process modeling and subthreshold device simulation

The dynamic switching characteristics of high-power GaAs Schottky and silicon p-i-n rectifiers are studied at various temperatures. Devices were first characterized to measure forward and reverse I-V, C-V, reverse breakdown voltage, and reverse-recovery performance. The same devices were characterized for turn on and turn off in switching circuits designed to study the dynamic switching performances under hard- and soft-switching conditions at different temperatures. Advanced two-dimensional (2-D) mixed device and circuit simulations were used to study the internal plasma dynamics under boundary conditions imposed by the circuit operation. It is shown that for hard-switching applications, GaAs Schottky power rectifiers exhibit significantly reduced switching power losses compared to silicon p-i-n rectifiers. For soft-switching applications, there is not a significant difference in the switching power losses for these two devices. Diode performance at elevated temperatures is measured and simulated, and temperature dependencies of switching and conduction power losses are analyzed.

By integrating the efforts in process, device and circuit simulations, this paper investigates the polysilicon-gate depletion effect (PDE) on performance of circuits composed of deep-submicron transistors. The DC and AC components of PDE on circuit performance are separated for the first time. The study delineates quantitatively the competing effect between the DC and AC PDE. Results of this study suggest the following: (i) PDE degrades circuit speed through dominance of the DC component in the competing effect. Reduction of gate oxide thickness lessens this DC PDE dominance behavior. (ii) Circuit speed degradation due to PDE becomes more significant during low-power operation. (iii) The above phenomenon in (ii) can be substantially improved by thinning the gate oxide thickness. >

The impact of the enhanced mobility of a strained-Si channel on the performance of sub-100 nm complementary metal oxide semiconductor (CMOS) circuits is investigated by the combination of device and circuit simulations, considering both velocity saturation and velocity overshoot effects. It is found that higher mobilities of strained Si become more advantageous with reducing the channel length. It is also pointed out that the increase in energy relaxation time in strained Si, in addition to higher mobility, is effective for the enhancement of the circuit performance. The evaluated performance of 50 nm strained-Si CMOS amounts to around 1.7 times that of bulk-Si CMOS.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present an extraction procedure of the above-threshold parameters of a modified level-15 model of hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs). This procedure is useful for model parameter extraction for short-channel devices, including the self-heating effect (SHE) and the nonsaturating drain current effect via the channel length modulation (CLM). The drain current formula of the AIM-Spice level-15 model was modified to include the nonsaturating drain current and SHE in the model. This procedure is also useful for devices in which the source–drain contact resistance <formula formulatype="inline"><tex Notation="TeX">$R_{sd}$</tex></formula> is comparable to, or greater than, the channel resistance, which is common in short-channel a-Si:H TFTs with a channel length of 10 <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> or less. We propose a modified integral function method for the extraction of contact resistance and threshold voltage. This method includes features of the ratio method and the integral function method. Using this modified integral function method, we extract both the threshold voltage <formula formulatype="inline"><tex Notation="TeX">$V_{t}$</tex></formula> and the series contact resistance <formula formulatype="inline"><tex Notation="TeX">$R_{sd}$</tex></formula> at the very beginning of the extraction process. When simulated data were used for extraction, <formula formulatype="inline"><tex Notation="TeX">$V_{t}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$R_{sd}$</tex></formula> extracted by our proposed method agreed with the true parameter values better than the parameters extracted by the integral function method or the ratio method. For a short-channel device with a significant SHE, the field-effect mobility <formula formulatype="inline"><tex Notation="TeX">$\mu_{ \rm FE}$</tex></formula> parameters were separately extracted for the linear and saturation regions, because <formula formulatype="inline"><tex Notation="TeX">$\mu_{\rm FE}$</tex></formula> was higher in the saturation region than that in the linear region, which is probably caused by the SHE-induced rise of channel temperature. The calculated <formula formulatype="inline"><tex Notation="TeX">$I$</tex></formula>–<formula formulatype="inline"><tex Notation="TeX">$V$</tex></formula> characteristics based on the extracted parameters fit the experimental data well in both the short- and long-channel devices. This suggests that the modified drain current model including the SHE and the nonsaturating drain current is valid; the proposed parameter extraction procedure is valid and may be implemented in the circuit simulator, such as AIM-SPICE, with some further improvement in the field-effect mobility formula when SHE is present. </para>

Electromagnetic (EM) simulators have already become established in the design of a variety of electromagnetic devices, such as MMICs (monolithic microwave integrated circuits), antennas, shields, electromechanical machines, and magnetic circuits. Such broad applicability results from the fact that the EM simulators are software packages for numerically solving the Maxwell’s fundamental electromagnetic field equations; for the same reason, and unlike some of the other simulators, they are independent of technology, models, foundry, and other such ephemeral considerations. Although designers have long carried out electromagnetic analysis of RF components and packages where necessary, the availability of commercial EM simulators1’2 since 1989 has made this task much more common, rapid, and easier. This development parallels the concurrent development of multi-chip module (MCM) technology for high-speed digital systems, as well as the front-ends of radio-frequency (RF) systems, such as receivers, transponders, transceivers, synthesizers, and transmit-receive modules. MCMs are a modern method of electronic packaging and integration that has the advantages of low-cost, compact size, and reliability. At low speeds/frequencies, the analysis, design, simulation, layout, and verification, of MCMs requires a number of software tools for computer-aided design (CAD), including process simulators, device simulators, circuit simulators, thermal simulators, and system simulators. For high-speed and RF MCMs, the design requirements make an additional CAD tool, namely EM simulator, indispensable.