Combined process modeling and subthreshold device simulation

A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1- mu m-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7 degrees implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator. >

: We prototyped Polyfet RF Device's 80V LDMOSFETs on bulk silicon substrates using advanced numerical two-dimensional (2D) finite-element semiconductor process and device simulators and showed excellent agreement between measured and simulated DC and RF parameters. This infrastructure was then used to develop a number of 40V LDMOSFET designs, both on bulk silicon and SOI material, and identify optimum device structures suitable for further development in Phase II. Our Phase I research has shown the SOI LDMOSFETs promise significant improvements in gain, noise figure, efficiency and manufacturing cost compared to bulk devices. These results are highly promising and provide the impetus for further investigation and development.

Nonzero implantation tilt angles are shown to cause an asymmetry in high-field effects, such as bipolar snapback and hot carrier injection, even when adequate source/drain overlap is achieved. This effect can cause large variations in a MOSFET's reliability, depending on its orientation and location within the wafer. Based on two-dimensional process and device simulations, it is shown that the Lightly Doped Drain (LDD) is more promising than the Graded Source/Drain (GSD) in avoiding these asymmetrical high-field effects at submicron dimensions. Guidelines are presented for the design of an optimized LDD structure, and substrate current is proposed as the best monitor for asymmetries in source/drain profiles.

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.

New combined method for calibrating the parameters of 2D technological and electrophysical models of "software package for two-dimensional process and device simulation - MicroTec-3.02" was suggested in this paper. This calibrating is realized on basis of high-accuracy 1D doping profiles in the channel and source-drain areas of MOS-transistors which were calculated by "FACT" software package, as well as volt-ampere characteristics of researched devices, that were really measured.

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation. >

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

The gate length and gate contour of a GaAs metal–semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior. GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter Cgs while gate contour affects Cgd. The breakdown voltage has strong dependence on gate contour and little dependence on gate length.

A two-dimensional numerical device simulator has been developed specially for the recessed gate 4H silicon carbide(4H-SiC) metal–semiconductor field-effect-transistor (MESFET). By combining numerical techniques, material physics, and measured device characteristics, we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field curves, and the Schottky barrier height. We have also enabled and used the new simulator to investigate breakdown voltage and thus predict operation limitations of the 4H-SiC device. Simulations indicate that impact ionization is relatively small in 4H-SiC, thereby leading to a very high breakdown voltage of 125 V in a 0.7 μm gate MESFET.

The importance of transient analysis in the design of floating-gate EEPROMs is demonstrated. Anomalous behavior, which was identified during transient measurements, has been simulated using HFIELDS, a general-purpose two-dimensional (2D) numerical device simulator. The corrective action that was taken at the time to eliminate the problem has been analyzed and explained using the simulation results. In addition, the simulator has been used to investigate 2D effects in the device due to process nonidealities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a compact model for metal oxide semiconductor (MOS) capacitors, based on a time-dependent solution for the surface potential. This enables modeling of the frequency dependence of MOS capacitors, which is not possible with existing compact models. The model is implemented in Verilog-A, and is verified against two-dimensional (2-D) numerical device simulations with DESSIS.

This paper describes the numerical implementation of Schottky boundary conditions in the basic module of the two-dimensional process and device simulator TRENDY developed at MESA Research Institute, University of Twente, The Netherlands. The results of simulation of a test structure are represented.

A numerical model for the simulation of ultraviolet sensitive ion-implanted 4H-SiC photodiodes is established. To explain the measured wavelength dependence of the photoresponsivity of such photodiodes, conventional simulation model was modified twofold. First, new experimental data on the optical properties of 4H-SiC were included into the model. Second, the doping dependence of recombination lifetimes was recalibrated, resulting in a stronger recombination of charge carriers in the ion-implanted region near the SiC surface. After the calibration of the model using experimental data, the model was applied for the optimization of the photodiode performance. An improvement of photoresponsivity by about 30% can be achieved by optimizing the thickness of antireflective layer. An improvement by more than 70% can be achieved by lowering doping level to $1\cdot 10^{14}$ cm $^{\mathrm {-3}}$ in the epitaxial layer of 4H-SiC diodes.

This volume contains the proceedings of the 10th edition of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2004), held in Munich, Germany, on September 2-4, 2004. The conference program included 7 invited plenary lectures and 82 contributed papers for oral or poster presentation, which were carefully selected out of a total of 151 abstracts submitted from 14 countries around the world. Like the previous meetings, SISPAD 2004 provided a world-wide forum for the presentation and discussion of recent advances and developments in the theoretical description, physical modeling and numerical simulation and analysis of semiconductor fabrication processes, device operation and system performance. The variety of topics covered by the conference contributions reflects the physical effects and technological problems encountered in consequence of the progressively shrinking device dimensions and the ever-growing complexity in device technology.