Combined Method for Two-Dimensional Modeling of MOS-transistors Parameters

A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.

Combined process modeling and subthreshold device simulation

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

The gate length and gate contour of a GaAs metal–semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior. GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter Cgs while gate contour affects Cgd. The breakdown voltage has strong dependence on gate contour and little dependence on gate length.

Nonzero implantation tilt angles are shown to cause an asymmetry in high-field effects, such as bipolar snapback and hot carrier injection, even when adequate source/drain overlap is achieved. This effect can cause large variations in a MOSFET's reliability, depending on its orientation and location within the wafer. Based on two-dimensional process and device simulations, it is shown that the Lightly Doped Drain (LDD) is more promising than the Graded Source/Drain (GSD) in avoiding these asymmetrical high-field effects at submicron dimensions. Guidelines are presented for the design of an optimized LDD structure, and substrate current is proposed as the best monitor for asymmetries in source/drain profiles.

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1- mu m-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7 degrees implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator. >

: We prototyped Polyfet RF Device's 80V LDMOSFETs on bulk silicon substrates using advanced numerical two-dimensional (2D) finite-element semiconductor process and device simulators and showed excellent agreement between measured and simulated DC and RF parameters. This infrastructure was then used to develop a number of 40V LDMOSFET designs, both on bulk silicon and SOI material, and identify optimum device structures suitable for further development in Phase II. Our Phase I research has shown the SOI LDMOSFETs promise significant improvements in gain, noise figure, efficiency and manufacturing cost compared to bulk devices. These results are highly promising and provide the impetus for further investigation and development.

This paper describes the numerical implementation of Schottky boundary conditions in the basic module of the two-dimensional process and device simulator TRENDY developed at MESA Research Institute, University of Twente, The Netherlands. The results of simulation of a test structure are represented.

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.

The article considers the issues of digital modeling of dynamic processes in the transmissions of transport vehicles. The purpose of this research was to develop an algorithm for numerical mathematical modeling of dynamic processes in the transmissions of transport vehicles using modern digital software packages. The method includes a systematic approach to the study of dynamic processes during switching, based on modeling the operation of the gearbox together with the internal combustion engine (taking into account its dynamic, speed and load characteristics). The order of application of the MATLab - Simulink, Simscape software packages for numerical simulation of dynamic processes is considered. Using the fundamental blocks of these applications, models of physical components are created: the internal combustion engine, friction clutches, gearboxes, elastic shafts, damping devices, and tractor power transmission control systems. A digital model of the tractor transmission is created, its design scheme is given, and the initial characteristics are set. It was used to simulate dynamic processes in the tractor gearbox. The main attention in this paper is paid to the application of the proposed method for calculating the dynamic processes in the gearbox during gear changes under load with forward and reverse switching, including the simultaneous use of several friction clutches.

A new commercial software package for the minimum-time optimal-control simulation of motorcycles, named OMS (Optimal Maneuver Simulation), is presented. OMS integrates a set of tried-and-tested components (vehicle and road models, solver) in a single software package that allows a team new to minimum-time simulation to kick-start this activity. A typical use case of OMS is performing a sensitivity analysis on some vehicle parameters to assess the effect of different vehicle configurations on the lap-time performance on a given track.

An update is provided of the software package for link simulation that were described in the January 1984 issue of this journal (P. Balaban, et al., ibid., vol.2, no.1, pp.1-8). The packages covered are SYSTID, TOPSIM, CHAMP, ICS, ICSSM, BLOSIM, and CLASS. Three new software packages are reviewed: MODEM, WCS, and BOSS. Recent trends in software packages for simulation-based analysis and design of communication links are also discussed. >

An SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS using a recessed source and a trench drain is proposed to reduce the on-resistance and increase the breakdown voltage. The recessed source structure is formed by v-groove etching and the trench drain structure is formed by RIE (Reactive Ion Etching). The characteristics of the proposed LDMOS are numerically calculated by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 36.5 V VLDMOS, the on-resistance of the proposed device is decreased by 41% compared with that of the conventional device.

A two-dimensional numerical device simulator has been developed specially for the recessed gate 4H silicon carbide(4H-SiC) metal–semiconductor field-effect-transistor (MESFET). By combining numerical techniques, material physics, and measured device characteristics, we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field curves, and the Schottky barrier height. We have also enabled and used the new simulator to investigate breakdown voltage and thus predict operation limitations of the 4H-SiC device. Simulations indicate that impact ionization is relatively small in 4H-SiC, thereby leading to a very high breakdown voltage of 125 V in a 0.7 μm gate MESFET.

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.