Optimization of 4H-SiC UV Photodiode Performance Using Numerical Process and Device Simulation

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.

Based on numerical device and process simulation, it is shown that enhancement of the boron diffusivity by as much as 300 times in the thin gate oxide results in a very shallow exponential p-type profile in the underlying silicon substrate. The effect of fluorine and phosphorus coimplantation into the p-type polysilicon gate is modeled by changes in the boron diffusivity in the gate oxide and segregation at the polysilicon-oxide interface. An inverse PMOS short-channel behavior in which the threshold voltage becomes more negative with decreasing channel length is modeled by two-dimensional boron segregation effects caused by the poly gate oxidation. >

Combined process modeling and subthreshold device simulation

In this article the impact of geometrical parameters of the dummy gate on capacitance characteristics for RF-LDMOS transistors is analyzed and studied by using a 2-D numerical TCAD process and device simulator. Firstly, the device structure and fabrication process are described. Then measured and simulated capacitance characteristics of the fabricated RF-LDMOS transistors are compared, confirming the effectiveness of the TCAD simulations. On the basis of this, further extensive simulations on the device capacitance characteristics for varying thickness of the oxide layer under and beside the dummy gate (tfox) and length of the dummy gate over n-drift region (Lf) are carried out. Based on these simulation results, the effects of the dummy gate on various capacitance components are analyzed and discussed, indicating that feedback capacitances can be effectively reduced by the introduction of the dummy gate to the device, nevertheless, at the expense of increased output and input capacitances. For this reason, the key geometry parameters of the dummy gate have to be traded off in order to optimize device design.

A numerical model of multilayer organic light-emitting devices (OLED) is presented in this paper which was consisted of electrical and optical model. The electrical model is based on the drift-diffusion equations. Multilayer organic heterojunctions were mostly considered in this work. A simulation course was programmed with MATLAB. The <i>I-V</i> characteristics obtained show a good agreement with experiment data. The optical model utilizes the optical interface effect, the EL spectrum was calculated with Alq₃ thickness of 40 nm, 50 nm and 60 nm, respectively. The Brightness- Voltage characteristics was simulated, the results and experimental data in the literature are in good agreement on the magnitude.

The current understanding of the relaxation and reconstruction of low-index cubic SiCsurfaces, as it derives from first-principles calculations, is briefly reviewed in comparisonwith surface-sensitive experimental data. The calculated structural properties are obtainedfrom ab initio total energy and grand canonical potential minimization in the framework ofthe local density and generalized gradient approximations of density functional theory.Characteristic surface structural properties are related to the surface electronic structureand to the ionicity of the underlying bulk crystal. For a number of cubic surfaces, there isgood agreement between first-principles results and the data. In other cases, mostnoticeably for Si-terminated SiC(001) surfaces, there is still considerable controversy withrespect to the atomic and electronic structure in both experiment and theory.

Integration of process, device and circuit simulation tools is desirable in modern process development and circuit design, as it allows rapid assessment of the impact of a new process or process change on circuit performance, [1]. This paper presents an efficient scheme for the extraction of MOSFET linear region SPICE level 3 parameters from numerical device simulations. Carrier concentrations, potential and mobility are used to derive a total of seven linear region parameters from three off-state bias points. This is in contrast to standard curve fitting techniques where twenty or, more on-state bias points would typically be used to obtain the required parameters.

Efficiency enhancement of ultra-thin Cu(In,Ga)Se2 solar cells: optimizing the absorber bandgap profile by numerical device simulations

: We prototyped Polyfet RF Device's 80V LDMOSFETs on bulk silicon substrates using advanced numerical two-dimensional (2D) finite-element semiconductor process and device simulators and showed excellent agreement between measured and simulated DC and RF parameters. This infrastructure was then used to develop a number of 40V LDMOSFET designs, both on bulk silicon and SOI material, and identify optimum device structures suitable for further development in Phase II. Our Phase I research has shown the SOI LDMOSFETs promise significant improvements in gain, noise figure, efficiency and manufacturing cost compared to bulk devices. These results are highly promising and provide the impetus for further investigation and development.

Roentgenographic Examination of Dental Gold Alloys

In recent past, there has been massive research in the field of organic electronics. Many novel techniques are proposed for improving the device and circuit performance. The use of the dual gate organic thin film transistor (DG-OTFT) provides one such technique to enhance the overall performance of organic devices and circuits. The DG-OTFT not only boosts the performance of the device and circuit but also makes them robust. This research paper analyzes the in-depth behavior of the DG-OTFT for top gate, bottom gate and dual gate modes of operation in terms of drive current, mobility, threshold voltage, sub-threshold slope and current on-off ratio. The observed results show higher drive current in the dual gate mode due to formation of two channels resulting in higher carrier injection. The electrical characteristics and performance parameters of DG-OTFT based on PDPP-TNT as organic semiconductor are evaluated and validated with the reported experimental results. The simulation results are in close agreement with experimental data. Consequently, the static and dynamic behavior of organic SR latch based on all p-type DG-OTFT is investigated using organic module of Atlas 2-D numerical device simulator.

The high-temperature performance of 4H-SiC ultraviolet avalanche photodiodes (APDs) in both linear and Geiger modes is extensively investigated. During the temperature-dependent measurements, a fixed bias voltage is adopted for the device samples, which is much more practical and important for high-temperature applications. The results show that the fabricated 4H-SiC APDs are very stable and reliable at high temperatures. As the temperature increases from room temperature to 425 K, the dark current at 95% of the breakdown voltage increases slightly and remains lower than 40 pA. In Geiger mode, our 4H-SiC APDs can be self-quenched in a passive-quenching circuit, which is expected for high-speed detection systems. Moreover, an interesting phenomenon is observed for the first time: the single-photon detection efficiency shows a non-monotonic variation as a function of temperature. The physical mechanism of the variation in high-temperature performance is further analyzed. The results in this work can provide a fundamental reference for researchers in the field of 4H-SiC APD ultraviolet detectors.

This paper reports a plasma post-treatment technique to improve the performance of GaN ultraviolet avalanche photodiodes (APDs). A BCl3-based plasma post-etching technique was developed to smooth the roughened GaN surface after inductively-coupled-plasma etching. Atomic-scale surface roughness around 0.278 nm rms and photoluminescence intensity more than doubled were achieved after the post-treatment. The surface smoothing technique was applied to the fabrication process of double-mesa structure GaN APDs grown on a sapphire substrate. Compared to the non-treated APDs, the post-treated GaN APDs show high field leakage current suppressed more than two orders and the average gain increased from 2 × 104 to 1 × 105, indicating the low surface damage after BCl3 plasma post-treatment. For the GaN APDs fabricated into a 3 × 3 array, the devices show uniform distribution of the breakdown voltages after the plasma post-treatment.

Hollow fiber membrane contactors (HFMC) have gained prominence in post-combustion CO2 capture applications due to their potential for high mass transfer rates, compactness, modularity and versatility. In this work, two pilot plant design have been proposed, an innovative solution which foresees the membrane contactor as CO2 absorption reactor, and a conventional one based on a packed column absorber. A one-dimensional model based on the resistance-in-series method has been developed for the membrane module and validated against experimental data from literature. The other process units have been simulated in Aspen Plus V11. According to the model results the membrane contactor unit is able to guarantee same levels of CO2 removal rates with improved energy performances compared to the conventional packed column absorber. In particular, if the same reactor volume is considered for the two absorber configurations, a reduction in the specific reboiler duty (SRD) of 8.5% is estimated. On the other hand, if the same liquid-to-gas (L/G) ratio is applied, the HFMC is able to guarantee a required reactor volume almost halved (45% reduction). These substantial improvements of the CO2 capture process could lead to lower investment cost and better economic indicators of the CO2 capture plant.

Models for the electron mobility in the three most important silicon carbide (SiC) polytypes, namely, 4H, 6H, and 3C SiC are developed. A large number of experimental mobility data and Monte Carlo (MC) results reported in the literature have been evaluated and serve as the basis for the model development. The proposed models describe the dependence of the electron mobility on doping concentration, temperature, and electric field. The low-field mobility in 4H SiC is much higher than in 6H and 3C in the doping range interesting for RF power transistors (10/sup 16/ cm/sup -3/ ...10/sup 18/ cm/sup -3/), whereas the saturation velocities in the three polytypes investigated are nearly the same (slightly above 2/spl times/10/sup 7/ cm/s at 300 K). The models developed can be easily incorporated into numerical device simulators.