Two-dimensional numerical analysis of floating-gate EEPROM devices

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.

This paper presents a compact model for metal oxide semiconductor (MOS) capacitors, based on a time-dependent solution for the surface potential. This enables modeling of the frequency dependence of MOS capacitors, which is not possible with existing compact models. The model is implemented in Verilog-A, and is verified against two-dimensional (2-D) numerical device simulations with DESSIS.

Combined process modeling and subthreshold device simulation

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

The gate length and gate contour of a GaAs metal–semiconductor field effect transistor (MESFET) device play important roles in determining the small signal circuit parameters and large signal breakdown voltage behavior. GaAs MESFETs with different gate lengths and gate contours were studied by the two-dimensional (2-D) semiconductor device simulations to investigate the dependence of small signal circuit parameters and breakdown voltage on gate length and gate contour. The results show that gate length affects small-signal circuit parameter Cgs while gate contour affects Cgd. The breakdown voltage has strong dependence on gate contour and little dependence on gate length.

: We prototyped Polyfet RF Device's 80V LDMOSFETs on bulk silicon substrates using advanced numerical two-dimensional (2D) finite-element semiconductor process and device simulators and showed excellent agreement between measured and simulated DC and RF parameters. This infrastructure was then used to develop a number of 40V LDMOSFET designs, both on bulk silicon and SOI material, and identify optimum device structures suitable for further development in Phase II. Our Phase I research has shown the SOI LDMOSFETs promise significant improvements in gain, noise figure, efficiency and manufacturing cost compared to bulk devices. These results are highly promising and provide the impetus for further investigation and development.

In this paper, a detailed performance comparative study is performed among AlGaN/GaN, InAlN/GaN and conventional AlGaAs/GaAs based high electron mobility transistor (HEMT) devices. The comparison analysis is executed using a non-linear two-dimensional T-CAD numerical device simulator. With the recent carrier transport advancements, our paper mainly focuses on superior electrical property and high electron velocity of Gallium Nitride (GaN) for HEMT device modeling. GaN-based HEMT devices exhibit maximum drain current as 2.8×10−4A, the threshold voltage of -1V, and unity current gain cut-off frequency of 75.4 GHz. The Silvaco T-CAD simulator greatly highlights the various HEMT device performance reports, targeting microwave frequency-based device applications.

A two-dimensional numerical device simulator has been developed specially for the recessed gate 4H silicon carbide(4H-SiC) metal–semiconductor field-effect-transistor (MESFET). By combining numerical techniques, material physics, and measured device characteristics, we are able to use the simulator to extract more information about the new material 4H-SiC, including the mobility, velocity-field curves, and the Schottky barrier height. We have also enabled and used the new simulator to investigate breakdown voltage and thus predict operation limitations of the 4H-SiC device. Simulations indicate that impact ionization is relatively small in 4H-SiC, thereby leading to a very high breakdown voltage of 125 V in a 0.7 μm gate MESFET.

The accuracy of an effective channel length/external resistance extraction algorithm for MOSFET's is assessed. This is accomplished by exercising the algorithm with current-voltage data generated by two-dimensional numerical device simulation; the extracted quantities are directly compared to their known counterparts as they exist in the cross section of the simulated device. Extracted effective channel length is found to be within 0.07 µm of the metallurgical channel length in both the conventional and LDD MOSFET's studied here. Extracted external resistance is found to be a reasonable first-order estimate of actual device resistance external to the metallurgical channel but is unable to supply proper information regarding the gate bias dependence of this quantity.

We report on the realization of an InGaP-GaAs-based double heterojunction bipolar transistor with high breakdown voltages of up to 85 V using an Al/sub 0.2/Ga/sub 0.8/As collector. These results were achieved with devices with a 2.8 μm collector doped to 6×10/sup 15/ cm/sup -3/ (with an emitter area of 60×60 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). They agree well with calculated data from a semi-analytical breakdown model. A /spl beta//R/sub SBI/ (intrinsic base sheet resistance) ratio of more than 0.5 by introducing a 150-nm-thick graded Al-content region at the base-collector heterojunction was achieved. This layer is needed to efficiently suppress current blocking, which is otherwise caused by the conduction band offset from GaAs to Al/sub 0.2/Ga/sub 0.8/As. The thickness of this region was determined by two-dimensional numerical device simulations that are in good agreement with the measured device properties.

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

We attempt to clarify the factors that regulate the propagation and structure of gravity currents through evaluation of idealized theoretical models along with two-dimensional numerical model simulations. In particular, we seek to reconcile research based on hydraulic theory for gravity currents evolving from a known initial state with analyses of gravity currents that are assumed to be at steady state, and to compare these approaches with both numerical simulations and laboratory experiments. The time-dependent shallow-water solution for a gravity current propagating in a channel of finite depth reveals that the flow must remain subcritical behind the leading edge of the current (in a framework relative to the head). This constraint requires that hf/d ≤ 0.347, where hf is the height of the front and d is the channel depth. Thus, in the lock-exchange problem, inviscid solutions corresponding to hf/d = 0.5 are unphysical, and the actual currents have depth ratios of less than one half near their leading edge and require dissipation or are not steady. We evaluate the relevance of Benjamin's (1968) well-known formula for the propagation of steady gravity currents and clarify discrepancies with other theoretical and observed results. From two-dimensional simulations with a frictionless lower surface, we find that Benjamin's idealized flow-force balance provides a good description of the gravity-current propagation. Including surface friction reduces the propagation speed because it produces dissipation within the cold pool. Although shallow-water theory over-estimates the propagation speed of the leading edge of cold fluid in the ‘dam-break’ problem, this discrepancy appears to arise from the lack of mixing across the current interface rather than from deficiencies in Benjamin's front condition. If an opposing flow restricts the propagation of a gravity current away from its source, we show that the propagation of the current relative to the free stream may be faster than predicted by Benjamin's formula. However, in these situations the front propagation remains dependent upon the specific source conditions and cannot be generalized.

This paper reports on the results obtained from a study of the performance and reliability characteristics of two low-voltage power MOSFET structures. Both structures were fabricated using ultrahigh cell density self-aligned refractory TiSi/sub 2/ gate and contact technology. In the power MOSFET structure with an integral Schottky diode (ISMOSFET), approximately 5% of the total number of cells were used for incorporating a Schottky diode in parallel with the parasitic PN-junction diode inherent in the MOSFET structure. Two-dimensional (2D) mixed device and circuit simulations were used to study the unclamped inductive switching (UIS) characteristics. It is shown that the ISMOSFET structure performs similarly to the MOSFET structure under UIS conditions. The former, however, results in more than 30% improvement in the reverse recovery performance with no degradation in the on-state power loss and off-state blocking voltage rating. The simulation results are shown to be in excellent agreement with the measured data. >

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50 nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.

An improved analytical model for lateral bipolar transistors is described that allows reproduction of anomalous effects often observed in lateral bipolar junction transistors (BJTs) arising from the presence of the gate electrode and a nonuniform doping profile in the base. The model also includes hybrid mode operation of the lateral BJT. Results obtained from this model are compared with 2-D numerical device simulations and measurements.