An accurate and scalable MOSFET aging model for circuit simulation

The reliability variation simulation methodology for advanced integrated circuit (IC) design is presented from an Electronic Design Automation (EDA) perspective. Reliability effects, such as hot carrier injection (HCI) and bias temperature instability (BTI), continue to be one of major concerns when devices scale down to smaller sizes. Reliability variability, considering process variation (PV) and aging variation (AV), is becoming critical for circuit reliability and yield. In this paper, we present and compare various reliability variability methodologies that incorporate process and aging variations for circuit simulation. Additionally, the correlation between PV and AV is analyzed. Finally, two representative circuits (ring oscillator and SRAM) are demonstrated with the reliability variation-aware simulation.

Very large scale integration (VLSI)‐based neuromorphic systems have been evolving quickly in recent years. These systems have been used in complex cognitive tasks such as image classification and pattern recognition. A neuromorphic encoder is an essential component in a neuromorphic system, which converts sensory data into spike trains. The advancement in CMOS technology nodes leads to various reliability issues. Bias temperature instability (BTI) and hot carrier injection (HCI) are major reliability issues in analog/mixed VLSI circuits. This paper implements a temporal neuromorphic encoder, and a corresponding mathematical model is derived for image processing applications. The relationship between an input image pixel value and output of the encoder, that is, interspike interval (ISI), is found to be exponential. The impact of BTI and HCI on the temporal neuromorphic encoder is analyzed. The degradation analysis revealed a loss of encoding functionality for which three mitigation techniques are discussed. Finally, a reliability‐aware neuromorphic encoder is proposed to minimize the effect of degradation over its lifetime. The power consumption of conventional and proposed reliability‐aware neuromorphic encoders is also presented.

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

Summary form only given. In order to continue technology scaling to meet future performance needs, multi-gate field effect transistors (MugFETs), are currently under investigation. MugFETs can be fabricated on silicon-on-insulator (SOI), and they are especially attractive because their three-dimensional structure enables excellent immunity to short channel effects, without significant changes to conventional CMOS fabrication techniques. One MugFET design of interest is known as the FinFET, where a hard mask is placed on the top surface of a fin structure to decouple it from the sidewall device operation (fig. 1). FinFETs can be fabricated with either the (110) sidewall surface or (100) sidewall where the crystal orientation of the fin sidewalls can have an impact on mobility and thereby provide a mobility boost based on orientation (fig. 1) [1,2]. In planar CMOS technologies, orientation dependent mobility enhancement has been demonstrated through the use of hybrid orientation technology (HOT) [3,4]. Here, hole (h <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) increases significantly when the channel orientation changed from Si(100) to Si(110). However, the electron (e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> ) mobility is severely degraded with the same orientation change. Therefore, there arises a need for HOT to take advantage of h <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> on Si(110) and e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> on Si(100). Our work demonstrates that the nMOS FinFET devices actually are not as severely degraded as planar nMOS, thereby mitigating the need to have orientation dependent CMOS FinFETs for μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> enhancement (fig. 2) [5]. However, a correlation of long channel mobility to short channel performance is necessary to confirm similar performance characteristics (fig. 3). Moreover, the implications of sidewall surface orientation on reliability issues such as hot carriers [6,7] and bias temperature instability [8,9] also need to be addressed. The surface orientation or fin structure may be more susceptible to degradation during stress. Possible causes include: Si interface bonds available for bond breakage [10] in the (110) plane, or structural properties that impact reliability differently than planar devices. In this work, we evaluate the dependence of FinFET sidewall orientation on performance (i.e., mobility and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) and reliability, where hot carrier injection and BTI are evaluated.

Tutorial 1: Memory Technology: Reliability Challenges and Future PerspectivesAbstract: Memory technologies occupy a huge share of the semiconductor market. Despite a large plethora of memory device concepts proposed over the years, only a restricted group of them has achieved large-scale production. Reliability is one of the main aspects limiting the adoption of a memory technology by the semiconductor industry. This tutorial aims at outlining the main reliability characteristics of memory devices and the characterization techniques to assess them. Representative case studies, namely RRAM and DRAM, are provided, to review the challenges to be overcome before a memory technology is widely accepted by the industry, and to describe how the causes of reliability failure are identified and mitigated. As the pursuit of innovative memory devices and architectures is relentless and fast-paced, this tutorial also provides future perspectives on memory technology and the related reliability challenges.Tutorial 2: Reliability of Energy-Efficient Phase Change Memory Based on Novel Superlattices and NanocompositesAbstract: Today’s computing systems are reaching fundamental limits with conventional materials like silicon, and with conventional layouts that separate memory and computing. To overcome these challenges, phase change memory (PCM) technology based on chalcogenides like Ge2Sb2Te5 (GST225) hold great promise for both data storage and neuromorphic computing. However, using conventional phase change materials, PCM operation requires large power consumption and suffers from resistance drift, limiting its potential for neuro-inspired and energy-efficient data storage. In this tutorial, we will address some of these challenges in PCM devices using novel phase change nanocomposite Ge4Sb6Te7 (GST467) and GST based phase-change superlattices. We will discuss the operation of energy-efficient and neuro-inspired PCM devices demonstrating gradual change of resistance states, low power switching, and multilevel operation with low resistance drift. We will also focus on the fundamental correlation between superlattice material characteristics and PCM device performance, important to ensure reliability and robustness of such technology for low power and brain-inspired computing.Tutorial 3: Brief Introduction to Device and Circuit ReliabilityAbstract: After a brief review of selected reliability basics, we discuss the main degradation mechanisms occurring in Field-Effect Transistors (FETs). These mechanisms include SILC (Stress Induced Leakage Current), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability), RTN (Random Telegraph Noise), and HCD (Hot Carrier Degradation) with the accompanying Self-Heating (SHE) and are linked with the underlying properties of defects. The effects of Mechanical Stress are also briefly reviewed. We then show that these defects play the essential role in many emerging technologies and applications, including CryoCMOS and 2D FETs, and are responsible for degradation variability in deeply-scaled devices. Finally, we show how device degradation can be accounted for in circuit simulations and demonstrate how in-depth knowledge of defect properties can be used to our advantage to design new devices and applications.Tutorial 4: 22FDX® RF/mmWave ReliabilityAbstract. The Fully Depleted Silicon on Insulator (FDSOI) technology was proven to be one of the best candidate for radio frequency (RF) and millimeter wave (mmWave) applications with lowest power consumption, lowest system footprint and the efficient electrostatic control of short channel effects. These advantages in addition with back-bias tuning and scalability knob offered by FDSOI technology give designers more freedom to explore and enhance their RF/mmWave designs. They need to push the devices at their limits to optimize and unlock best competitiveness for their IPs/designs. It results in high voltage/current stress to the devices, challenging standard technology qualification reliability models and their coverage. This tutorial will offer an overview about 22FDX® reliability effort to support the RF/mmWave design. It will include Non Conducting hot carrier injection (NCHCI) studies, off-state TDDB modeling, HCI Low Vgs modeling, Safe Operating Area methodology based on TDDB & RF/mmWave waveform analysis. The waveform analysis provides a base for assessing RF operation based on all DC reliability models and helps sizing critical RF/mmWave IPs for safe product lifetime, reducing design iterations to final product.

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.

In advanced technology nodes, Bias Temperature Instability (BTI) has emerged as a prominent reliability concern. The worst-case effects of BTI occur during specific workload phases in which flip-flops on a critical path do not switch their logic values for a long duration. These inactive flip-flops in the circuit experience accelerated workload-dependent static-BTI stress. The aging effect of static BTI for a few hours has been shown to be equivalent to one year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate static-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, we propose a runtime monitoring method to raise a flag when a timing-critical flip-flop experiences severe static-BTI stress. To reduce the monitoring costs, we select a small representative set of flip-flops offline based on workload-aware correlation analysis and these selected flip-flops are monitored online for static aging phases. Our experiments conducted on two processors show that, less than 0.5% of the total number of flip-flops is required to be selected as representative flip-flops for S-BTI stress monitoring.

In the development of MOSFETs first ‘Hot Carrier Injection’ (HCI) played an important role for reliability aspects [1,2]. With new shrinked process generations and nitrided gate oxides additionally the ‘Bias Temperature Instability’ (BTI) raised and became the most critical mechanism. Some publications even claim that HCI is negligible in main-stream applications [3–6]. But is this statement generally true or is it the result of a partial view? This paper will discuss the area of conflict regarding the importance of N/PBTI and HCI. Some typical examples will illuminate different fields of applications with one dominating damage mechanism. Specific characteristics of these circuits and operation conditions leading to an outbalance of HCI or Negative-/Positive-BTI will be carved out. Finally it will be evaluated if a general trend is observable.

Plasma-induced damage (PID) and bias temperature instability (BTI) are inevitable reliability issues that degrade the performance of transistors. In this study, PID and BTI, depending on the type of antenna layer, are evaluated in current-starved ring oscillators (ROs) to separate degradations in PMOS and NMOS transistors in a 65 nm silicon-on-insulator (SOI) process. Oscillation frequencies of ROs fluctuate with the performance of MOSFET switches between power/ground rails and virtual power/ground nodes. The initial frequencies of ROs with PMOS switches having antennas on upper layers decrease. However, those with NMOS switches become higher than those without PID because high-k dielectrics are damaged by positive charges. The degradation induced by negative BTI (NBTI) in PMOS is 1.5 times larger than that induced by positive BTI (PBTI) in NMOS. However, both NBTI- and PBTI-induced degradations are the same among different antenna layers. The frequency fluctuation caused by PID is converted to threshold voltage shifts by circuit simulations. Threshold voltages shift by 8.4 and 11% owing to PID in PMOS and NMOS transistors, respectively.

Bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD) degrade the performance of circuits, such as FinFET-based SRAMs. In this paper, a unified modeling methodology is applied for SRAM reliability degradation due to BTI and HCI, which are implemented with a time-dependent threshold voltage model, and GOBD which is implemented with a comprehensive current model. The applicability of degradation models is verified through fitting and comparison with the measured results. SRAM cell lifetime due to different mechanisms is calculated with Monte Carlo simulations to determine the performance degradation. The combined lifetime distribution and failure probability of an SRAM is further analyzed while considering the effect of Error Correcting Codes (ECC). Based on the different degrees of sensitivity, the potential of designing optimal accelerated life tests due to different failure mechanisms is discussed.

Particle filter approach to lifetime prediction for microelectronic devices and systems with multiple failure mechanisms

Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing moderate increase in failure rate of CMOS designs. Conventional analog and digital circuits typically employ feedback control for system stability or Dynamic Voltage Scaling (DVS) to optimize power performance respectively. For such closed loop topologies, the degradation rate can be dramatically accelerated, leading to destructive consequences. To identify such catastrophic phenomenon, this work (1) presents accurate simulation framework and aging models for BTI and CHC accounting underlying physics. Complete methodology is validated with 28 nm and 65 nm silicon data. (2) Investigates Bias Runaway, a rapid increase of gate-drain voltage of a bias circuit in analog/mixed signal (AMS) circuits. Along with silicon evidence, critical boundary condition and design trade-offs for bias runaway are also explored with technology scaling. (3) DVS induced acceleration in failure rate of logic circuits under NBTI and PBTI is demonstrated. Overall, this work identifies key issues to the stability of feedback systems, which is vitally important for reliable IC designs.

Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.

We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry.

For this work we have developed a model based flow for designing AlGaN/GaN power bars, taking into account the physics of the GaN HEMT architecture.. A link is generated between TCAD simulation and circuit simulations for GaN HEMT devices. A scalable compact model was developed, with analytical models for the extrinsic interconnect parasitics and access resistances. This modeling approach allows simulation of large area power bars based on TCAD simulations, and is, to the best of our knowledge, the first time that such a modeling approach is presented for GaN devices.