Accelerated Aging in Analog and Digital Circuits With Feedback

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

Although CMOS technology scaling has proceeded to sub-20nm nodes, FinFET devices are considered as the technology-of-choice for sub-20nm technology nodes due to the improved gate control [1]. On the other hand, voltage scaling provides us an energy efficient solution to the VLSI design, such as the near-threshold computing technique [2]. This work investigates the performance and energy consumption of LEON3 processor under technology and voltage scaling. Specifically, in order to study the impact of technology and voltage scaling, this work (i) develops 7nm gate length FinFET, ITRS 7nm FinFET (with 11nm actual gate length), ITRS 16nm CMOS, and ITRS 22nm CMOS Verilog-A device models using Synopsys TCAD tools [3], (ii) builds up the standard cell libraries using the developed Verilog-A models for the four previously mentioned technology nodes under a set of different supply voltage levels (i.e., from near-threshold to super-threshold), and (iii) synthesizes LEON3 processor (datapath plus L1 and L2 caches) using the developed standard cell libraries to compare the impact of technology and voltage scaling on the performance and energy consumption of LEON3 processor.

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.

Bias temperature instability (BTI) has become one of the major concerns in reliable circuit design in advanced CMOS nanometer technology. It can have a significant impact on the performance of analog building blocks. To understand the effect of BTI in analog circuits, an accurate measurement of circuit parameter degradation by BTI has become very necessary. This paper proposes a measurement scheme of the input offset degradation of an operational transconductance amplifier (OTA) due to the BTI effect. Conventional offset measurement techniques do not take into account the BTI recovery. Therefore, the proposed scheme is targeted to measure degradation during the stressing to avoid relaxation. The concept behind the scheme is to present the offset degradation as a function of the propagation delay degradation. Simulation results are shown for the measurement circuit.

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.

The vast majority of the existing studies on GC-eDRAM focus on implementation in mature technology nodes (most often 0.18 μm CMOS and no lower than 65 nm CMOS) and at nominal supply voltages. This chapter studies the suitability of GC-eDRAM beyond these design spaces by analyzing aggressive technology scaling, down to 28 nm CMOS, and aggressive supply voltage scaling, all the way to the subthreshold (sub-VT) domain. First, the analytical retention time model developed in Chap. 3 is validated for a scaled 28 nm CMOS node. Second, a conventional 2T GC topology is optimized for sub-VT operation. Simulations show successful sub-VT operation for a 2T GC-eDRAM array in 0.18 μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40 nm CMOS can be operated successfully down to the near-VT domain, while simultaneous aggressive technology and voltage scaling to the sub-VT domain are not recommended.

As technology scales down, the leakage energy accounts for more portion of total energy in a cache. Applying the Dynamic Voltage Scaling(DVS) to a cache, which is called a drowsy cache, is known as one of the most efficient techniques for reducing leakage energy in a cache. However, it increases the Soft Error Rate(SER) and many researchers began to doubt the reliability of a drowsy cache. In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores read-only data, rarely incurring unrecoverable errors. In the I-cache, the soft error can be recovered by re-fetching from the lower level memory. Second, the effect of soft errors on performance is negligible, because the SER is extremely low. Additional, considerable percentage of soft errors do not harm the performance. In this paper, the evaluation results show that the drowsy I-cache rarely increases unrecoverable errors and negligibly degrades the performance.

Analyzed herein is the effect of different germanium (Ge) concentrations on negative bias temperature instability (NBTI) and channel hot carrier (CHC) degradations in high-performance Si1-xGex pMOSFETs. It is shown that higher concentrations result in less NBTI degradation due to the increased barrier height between the SiGe and high-k dielectric interface, but it causes greater CHC degradation due to the decreased channel bandgap with higher Ge concentrations. Therefore, the tradeoff between NBTI and HC degradations for different Ge concentrations should be considered when developing high-performance Si1-xGex pMOSFETs.

Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltagecontrolled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling.

Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equation solving. However, analog computing also comes with drawbacks such as its sensitivity to process variation and noise, limited scalability, programming difficulty, and poor compatibility with digital circuits and design tools. We propose to leverage the strengths of analog circuits and avoid its weaknesses by using digital circuits and time-encoded computation. Time-encoded circuits also operate on continuous data but are implemented using digital circuits. We propose a novel scalable general purpose analog processor using time-encoded circuits that is well suited for emerging applications that require high numeric precision. The processor’s datapath, including time-domain register file and function units are described. We evaluate our proposed approach using an implementation that is simulated with a 0.18µm TSMC process and demonstrate that this approach improves the performance of a scientific benchmark by 4x compared against conventional analog implementations and improves energy consumption by 146x compared against digital implementations.

Horizontally stacked nanosheet gate-all-around (NS GAA) devices enable area scaling of transistor technology, while providing improved electrostatic control for FinFETs over a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. A typical NS process integration scheme (Fig 1) involves several key components that control device performance: the epitaxial SiGe/Si superlattice; the inner spacer (IS) module; and channel release (CR), which is part of the replacement metal gate (RMG) module [1-10]. Integration of each of these components presents significant challenges, all of which are addressed with our highly-selective gas phase etch processes as discussed in this paper.For IS indent, the SiGe etch process needs to have good depth control to provide well-optimized overlap capacitance and R on [9]. The process also needs excellent selectivity to prevent Si extension (T ext) thinning, which would increase external resistance. Furthermore, minimal etch-front rounding during the IS SiGe etch is necessary to prevent etch paths during CR that would damage the source/drain (S/D) epitaxy [4, 9]. We have developed two novel gas phase SiGe etches and characterized their properties on blanket films, multilayers (ML) and integrated NS structures. Understanding the etch properties enables careful optimization of the IS etch to address the integration challenges. Process A selectivity is greater than 100:1 on fully integrated structures, and is independent of Ge%. Process A selectivity is 4x better than Process B (Fig. 2(a, b)). Etch front rounding is quantified by “d/t”, where d /t = 100% for the ideal square profile (Fig. 3). Process B has a better IS profile (d /t ~ 82%) than Process A (d /t ~ 61%). We attribute this improvement to the smaller SiGe etch rate (ER) sensitivity to Ge% of Process B. In practice, the IS profile is limited by Ge diffusion at the Si-SiGe interface in the NS superlattice driven by anneals prior to IS etch (Fig. 4) [3-5, 9]. For Process B, the IS etch profile (d /t ~ 82%) matches closely with the simulated diffusion profile, indicating a highly optimized IS etch process. Although Process A has better selectivity, Process B is the best process for IS indent; its selectivity is sufficient to deliver good T ext while providing a better etch front for S/D protection during CR.For CR, high selectivity to Si is critical to minimize Si channel surface roughness and Si thickness (T Si) loss, which leads to mobility degradation, high channel resistance (R ch) and T Si variability between short channel and long channel (LC) devices and different NS width (W NS). The process also needs etch SiGe completely for small SiGe suspension thicknesses (T sus) without becoming self-limited to enable a wide range of W NS in LC devices. We have developed three SiGe etch processes with selectivities ranging between 100:1 to greater than 800:1, with peak ERs at about 30% SiGe -- a typical value for the NS structures – and Si channel RMS roughness ~0.3Å (Fig. 2 (b)) [9]. As confirmed by EDX (Fig. 5), this highly selective process completely removes all Ge from the Si channel, including the diffused Ge at the Si-SiGe interface resulting from anneals post NS ML deposition. This leaves behind a pristine Si channel, which is important for low Dit. The resulting T Si thinning is consistent with theoretical simulation of Ge diffusion (Fig 4, 5) [4]. As a result of higher SiGe etch selectivity, Processes A and C result in minimal corner rounding and T Si loss compared to Process B (Fig. 6). nFET R on for Processes A and C is ~10% better than Process B for W NS = 20nm (Fig. 7(a)), which translates to ~10% improvement in R ch (Fig. 7 (b)), driven by a similar improvement in peak transconductance (gm max) (Fig. 7 (c)). Therefore, we can attribute the primary component of the improvement in R on largely from higher effective sheet width (W eff) with Processes A and C. Correspondingly, breakdown voltage and bias temperature instability (BTI) also improve with Processes A and C, with reduced variability in BTI (data not shown).IS and CR processes have unique etch requirements. Thus the SiGe etch needs to be carefully optimized for IS and CR separately. Processes A and C are both well-suited for CR, while Process B is better for IS. These processes address the challenges discussed previously, maximizing device performance. The high structural integrity provided by these processes enables improved W eff, enhanced gm max, higher I d, reduced variability in L g, lower R on and constant V t across W NS, thus facilitating higher yield, for scaling of future logic technology nodes. Figure 1

Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 × 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift.

We present ABCD-NL, a technique that approximates non-linear analog circuits using purely Boolean models, to high accuracy. Given an analog/mixed-signal (AMS) system (e.g., a SPICE netlist), ABCD-NL produces a Boolean circuit representation (e.g., an And Inverter Graph, Finite State Machine, or Binary Decision Diagram) that captures the I/O behaviour of the given system, to near SPICE-level accuracy, without making any apriori simplifications. The Boolean models produced by ABCD-NL can be used for high-speed simulation and formal verification of AMS designs, by leveraging existing tools developed for Boolean/hybrid systems analysis (e.g., ABC [1]). We apply ABCD-NL to a number of SPICE-level AMS circuits, including data converters, charge pumps, comparators, non-linear signaling/communications sub-systems, etc. Also, we formally verify the throughput of an AMS signaling system - modelled in SPICE using 22nm BSIM4 transistors, Booleanized with high accuracy using ABCD-NL, and property-checked using ABC.

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability at both time zero and after NBTI aging increases. The time0 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability. This paper focuses on the bias temperature instability stress-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability and the trend across several technology generations. The remarkable correlation of aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.