Impact of technology and voltage scaling on LEON3 processor performance and energy

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.

The vast majority of the existing studies on GC-eDRAM focus on implementation in mature technology nodes (most often 0.18 μm CMOS and no lower than 65 nm CMOS) and at nominal supply voltages. This chapter studies the suitability of GC-eDRAM beyond these design spaces by analyzing aggressive technology scaling, down to 28 nm CMOS, and aggressive supply voltage scaling, all the way to the subthreshold (sub-VT) domain. First, the analytical retention time model developed in Chap. 3 is validated for a scaled 28 nm CMOS node. Second, a conventional 2T GC topology is optimized for sub-VT operation. Simulations show successful sub-VT operation for a 2T GC-eDRAM array in 0.18 μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40 nm CMOS can be operated successfully down to the near-VT domain, while simultaneous aggressive technology and voltage scaling to the sub-VT domain are not recommended.

Over the past decade, process parameter variations have been one of the key design challenges. At circuit level of abstraction, process parameter variations cause deviation in the design specifications which threaten the parametric yield, resulting cost implication on the semiconductor industry. Post-silicon tuning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) are the most commonly used techniques to mitigate the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we first examine the effect of process parameter variations on parametric yield loss. Further, we propose a framework that integrates ABB and DVS techniques to effectively mitigate the impacts of process parameter variations even for sub-45nm CMOS technology. We test the proposed approach w.r.t. Hybrid Redundant Multiply-and-Accumulate (HR-MAC) unit, however the proposed approach can be utilized for any digital circuit.

Negative capacitance field-effect transistor (NCFET) is one of the very promising emerging technologies that may replace existing CMOS technology in the future. This is due to its ability to push the sub-threshold swing of transistors to below 60 mV/decade, which what fundamentally limits voltage scaling in conventional CMOS technology and what has led in the past to the discontinuation of Dennard’s scaling. In this chapter, we demonstrate how NCFET technology can reshape the future of many-core systems—especially when it comes to thermally constrained processors. Compared to conventional CMOS technology, NCFET technology allows processors (1) to be clocked at higher frequency without any increase in the power density or (2) to operate at lower voltages, without sacrificing performance requirements. The latter leads to a significant power saving that plays a major role in increasing the total number of processor cores that can be simultaneously powered on without exceeding the predetermined thermal constraints. In addition, we demonstrate how NCFET technology makes the leakage power in processors increase, instead of decrease as in conventional CMOS technology, when voltage is scaled down. This fundamentally breaks down the core assumption of all existing power management techniques. Hence, novel runtime power management techniques need to be devolved in which such a new inverse leakage-voltage dependency is carefully considered. Otherwise, the efficiency of NCFET-based processors cannot be optimized. In this chapter, we also demonstrate the first NCFET-aware dynamic voltage scaling that optimizes the power of processor while taking the inverse leakage-voltage dependency into account.KeywordsMany coresEnforcementNon-functional requirementsReal-timeCentralizedDistributed

As technology scales down, the leakage energy accounts for more portion of total energy in a cache. Applying the Dynamic Voltage Scaling(DVS) to a cache, which is called a drowsy cache, is known as one of the most efficient techniques for reducing leakage energy in a cache. However, it increases the Soft Error Rate(SER) and many researchers began to doubt the reliability of a drowsy cache. In this paper, we show that the instruction cache(I-cache) can adopt the DVS without reliability problems for several reasons. First, an I-cache always stores read-only data, rarely incurring unrecoverable errors. In the I-cache, the soft error can be recovered by re-fetching from the lower level memory. Second, the effect of soft errors on performance is negligible, because the SER is extremely low. Additional, considerable percentage of soft errors do not harm the performance. In this paper, the evaluation results show that the drowsy I-cache rarely increases unrecoverable errors and negligibly degrades the performance.

With ever-scaling VLSI technology, the leakage is becoming an increasingly serious concern when addressing the power consumption problem for next-generation real-time embedded systems. Dynamic voltage scaling (DVS) is efficient in reducing the dynamic energy consumption of a CMOS processor. However, methods that employ DVS without considering the leakage current are quickly becoming less effective in reducing the processor's overall energy consumption. To be globally energy-efficient, the processor may have to run at a higher-than-necessary speed, which will cause a large number of idle intervals. While the processor can be shut down during these idle intervals to save energy, this process may incur significant timing and energy overhead. In this paper, we propose a DVS scheduling technique for fixed-priority hard real-time systems that can judiciously merge the short, scattered idle intervals into longer ones to reduce the shut-down overhead. The proposed technique has very low online computation complexity and can be readily incorporated with a variety of DVS scheduling techniques. Experimental results demonstrate that proposed technique can reduce the number of idle intervals and the overall energy consumption significantly more than conventional scheduling techniques.

Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies. The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. With a power budget of <; 20 mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) and complex digital processing in current fabrication technologies. In this paper, various designs and architectures for each component of an ADC-based receiver and their performance trade-offs are discussed. The design requirement of an ADC and digital processing can be relaxed with the aid of simple mixed-mode circuitry. More complex digital processing techniques are becoming feasible with the scaling of CMOS technology. However, the improvement from scaling is limited by the substantial leakage current, and the rate of improvement is slowing beyond 32 nm technology node.

Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltagecontrolled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling.

Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing moderate increase in failure rate of CMOS designs. Conventional analog and digital circuits typically employ feedback control for system stability or Dynamic Voltage Scaling (DVS) to optimize power performance respectively. For such closed loop topologies, the degradation rate can be dramatically accelerated, leading to destructive consequences. To identify such catastrophic phenomenon, this work (1) presents accurate simulation framework and aging models for BTI and CHC accounting underlying physics. Complete methodology is validated with 28 nm and 65 nm silicon data. (2) Investigates Bias Runaway, a rapid increase of gate-drain voltage of a bias circuit in analog/mixed signal (AMS) circuits. Along with silicon evidence, critical boundary condition and design trade-offs for bias runaway are also explored with technology scaling. (3) DVS induced acceleration in failure rate of logic circuits under NBTI and PBTI is demonstrated. Overall, this work identifies key issues to the stability of feedback systems, which is vitally important for reliable IC designs.

Low power memories continue to be an important topic for low power digital design, especially in light of the recent focus on green products. Voltage scaling for some time was a natural part of technology scaling, which automatically resulted in power reduction. For sub-100nm technologies it has been difficult to reduce active power consumption for SRAMs, because the amount of memory in digital ICs is still increasing and the memory bit cell does not allow a lower supply voltage without a severe area penalty. However, voltage scaling is not a goal in itself, and a variety of techniques exist to achieve low power. This paper gives an overview of the trends in technology scaling and its impact on low power memory design. The most important techniques that are used to make low power SRAM are discussed, and system level considerations are given, including trade-offs on the selection of SRAM and DRAM. For advanced technologies, SRAM variability is an important topic. Lowering the supply voltage to save power increases the sensitivity of SRAM to variability and reduces its robustness. Simulation approaches used to guarantee high yield even for large amounts of SRAM are discussed. A combination of these methods and techniques helps to achieve low power, yet robust systems.

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier

Evaluation of variability using Schmitt trigger on full adders layout

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.

SummaryScheduling on dynamic voltage and frequency scaling enabled processors to determine the Pareto‐optimal solutions with optimized makespan and energy consumption demands faster multi‐objective scheduling algorithms. In general, the problem of multi‐objective optimization, ie, finding the Pareto‐optimal solutions to optimize two or more QoS parameters, has been proven to be an NP‐complete problem. In this work, we propose a novel energy‐efficient quantum‐inspired stochastic Q‐HypE algorithm to schedule the batch‐of‐stochastic‐tasks (BoT) on DVFS‐enabled processors with the aim to optimize the makespan of BoT as well as the energy consumption of processors. The stochastic processing times of tasks are drawn from independent probability distributions. The proposed Q‐HypE algorithm evolves from combined characteristics of quantum computing and a hypervolume based multi‐objective optimization HypE algorithm. The proposed Q‐HypE algorithm simultaneously minimizes the makespan and energy consumption of the Pareto‐optimal solutions whereas the dynamics of quantum computing accelerate the process of HypE to further minimize the overheads of hypervolume estimation. Experimental results reveal the effectiveness of the proposed Q‐HypE algorithm both in terms of the number and quality of solutions offered.