Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems

Moore’s Law scaling has last for almost half century, leading to a tremendous performance/area improvement and cost reduction. Unfortunately, in the past decade, severe challenges have been faced by the CMOS technology as the technology node enters sub-100nm region. To sustain the growing transistor performance and density, many novel device technologies are proposed in the past decade to augment or even replace the conventional Si CMOS technology with Cu interconnect. For the device innovation, ever since the discovery of graphene with excellent physical and electrical properties, much interest has been drawn in the electron-device community and graphene-based FETs have been introduced. Based on the property of the angular dependent transmission probability of electrons observed in GPNJs, an enhanced device structure is presented. More elaborate physical models are also developed to better evaluate the upper limit of delay and power consumptions of GPNJ circuits, including ON resistance, leakage current, contact resistance, and footprint area. For the low-power applications, TFETs show promise in overcoming the power wall faced by thermionic FETs by allowing significant reduction in the supply voltage. The analytical device-level models for TFETs are developed to efficiently evaluate the overall system-level metrics. It is demonstrated that the IV characteristics of a TFET behaves like a Si CMOS switch, but it provides much lower leakage current and ultra-low supply voltage at the cost of low ON current. For the interconnect technology, as the conventional Cu interconnect scales, the resistance per unit length increases dramatically because of 1) the smaller cross-sectional area and 2) the severe size effects at sub-20nm nodes. To alleviate the interconnect challenge, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed and benchmarked against their copper counterpart in terms of energy and energy-delay product. Alternatively, carbon-based interconnects, such as graphene sheets and carbon nanotubes, are also potential candidates because of their outstanding electrical properties. However, graphene is a two-dimensional structure, and increasing the interconnect pitch does not lower the resistance as fast as it does in copper interconnects. Hence, comparing graphene and copper interconnects strongly depends on the interconnect pitch. As a result, system-level analyses are essential to better understand and evaluate the overall benefits of graphene interconnects. Different from existing system-level performance simulators that are based on cycle-accurate simulations, the present methodology employs three hierarchies of compact analytical models on material, device and interconnect, and system levels, respectively. Significant acceleration is achieved in the simulation speed, making multi-parameter optimization feasible. This run-time efficiency is crucial because many novel device concepts have fundamentally different operational principles, and their on/off currents and input capacitances vary drastically in accordance with their design parameters. This methodology allows technologies to evaluate various trade-offs among key design parameters and to maximize the overall chip throughputs or energy efficiencies of processors in a highly efficient way. For the validation of the proposed methodology, simulation results are compared and well matched with eight commercially available Intel multi-core processors across three technology generations from 65nm to 32nm technology nodes. For the GPNJ-based processors, the proposed design methodology is applied to efficiently perform device-, circuit-, and system-level co-optimization. For given power density and die size area budgets, various device-level parameters, including supply voltage, control voltage, gap distance, and oxide thickness, are optimized for a GPNJ core, where 2.1X throughput improvement is observed for a sharp-corner GPNJ core. This advantage is predominantly because of the smaller output resistance, which reduces both device and interconnect delay and saves the power for repeaters. For the TFET based processors, the results indicate that TFETs have excellent performance at the low power density range due to the low supply voltage. The limitations imposed by the interconnects and the large leakage current at high supply voltage restrict the driving current, leading to a lower performance of the TFETs at a high power density. For the emerging interconnect technology, the proposed Al-Cu hybrid interconnect technology is evaluated by replacing short narrow local signal interconnects by Al interconnects. Six interconnect architecture options are analyzed and their optimal aspect ratio and chip frequency are predicted for five technology generations. The optimization and benchmarking results indicate that the potential improvement in chip clock frequency can be between 50 to 100% for the 7nm technology node. A comprehensive optimization/benchmarking is also performed for the multi-layer graphene interconnects. The results show that a single core using graphene interconnects have a higher throughput within the same power density and die size area because of the power saving offered by the low capacitance graphene interconnects.

The retrograde p-well CMOS technology utilizes a single high-energy boron implant to produce a self-aligned channel stop and an extremely shallow, low sheet-resistance p-well while maintaining controllable, low n-channel threshold voltages. Conventional CMOS technologies are limited by Gaussian profiles where surface concentration, sheet resistance, and junction depth are directly coupled and low threshold voltages require either deep junctions or high sheet resistance. The retrograde p-well peak charge resides 1µ below the surface which lowers npn-beta from conventional values of 500-1000 to 30- 50 and allows spacing between n- and p-channel devices to be reduced from 12-15µ to 3-6µ. This all-implanted CMOS technology has been developed, fully characterized and modeled for devices with electrical channel lengths below 2µ. Ring oscillators have, a 700psec. stage delay and a 1K RAM test structure shows a 3.7 times density improvement, lower latch-up susceptibility, lower defect density, and higher performance than the same RAM conventionally processed.

Although CMOS technology scaling has proceeded to sub-20nm nodes, FinFET devices are considered as the technology-of-choice for sub-20nm technology nodes due to the improved gate control [1]. On the other hand, voltage scaling provides us an energy efficient solution to the VLSI design, such as the near-threshold computing technique [2]. This work investigates the performance and energy consumption of LEON3 processor under technology and voltage scaling. Specifically, in order to study the impact of technology and voltage scaling, this work (i) develops 7nm gate length FinFET, ITRS 7nm FinFET (with 11nm actual gate length), ITRS 16nm CMOS, and ITRS 22nm CMOS Verilog-A device models using Synopsys TCAD tools [3], (ii) builds up the standard cell libraries using the developed Verilog-A models for the four previously mentioned technology nodes under a set of different supply voltage levels (i.e., from near-threshold to super-threshold), and (iii) synthesizes LEON3 processor (datapath plus L1 and L2 caches) using the developed standard cell libraries to compare the impact of technology and voltage scaling on the performance and energy consumption of LEON3 processor.

Novel low‐power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re‐pull up the low swing voltage to full swing, innovated high‐speed, crosscoupled latch voltage receiver circuits are proposed. In applications having high load capacitance due to long interconnections, novel repeater circuits, based also on low swing voltage technique, are introduced. The difference between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.

As CMOS technology has a scaling limitation in deep nanometer technologies, the best alternative for CMOS technology is a Quantum - Dot Cellular Automata (QCA) technology. Quantum dot Cellular Automata has the combined nature of both quantum mechanics and cellular automata. The QCA technology has many advantages than transistor based technology such as small size, high speed, and low power consumption. The working principle of QCA technology is at the molecular level. In conventional CMOS technology, transistors are used to create a logic gate. But in QCA technology, QCA cells are used to create logic gates and wire. The basic logic elements are an inverter and the majority gate. By using these elements many of the combinational and sequential circuits are created. In this brief, we propose the binary up counter using T flip flop. 2 bit and 3 bit Counters are implemented using the above mentioned QCA technology. The layout was designed and the functionality of the counter circuit was verified using QCADesigner tool.

Negative Capacitance Field-Effect Transistor (NCFET) has recently attracted significant attention. In the NCFET technology with a thick ferroelectric layer, voltage reduction increases the leakage power, rather than decreases, due to the negative Drain-Induced Barrier Lowering (DIBL) effect. This work is the first to demonstrate the far-reaching consequences of such an inverse dependency w.r.t. the existing power management techniques. Moreover, this work is the first to demonstrate that state-of-the-art Dynamic Voltage Scaling (DVS) techniques are sub-optimal for NCFET. Our investigation revealed that the optimal voltage at which the total power is minimized is not necessarily at the point of the minimum voltage required to fulfill the performance constraint (as in traditional DVS). Hence, an NCFET-aware DVS is key for high energy efficiency. In this work, we therefore propose the first NCFET-aware DVS technique that selects the optimal voltage to minimize the power following the dynamics of workloads. Our experimental results of a multi-core system demonstrate that NCFET-aware DVS results in 20% on average, and up to 27% energy saving while still fulfilling the same performance constraint (i.e., no trade-offs) compared to traditional NCFET-unaware DVS techniques.

Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connect DVS blocks to one of the available VDD supplies. While power switches have been analyzed extensively for leakage power gating, proper design of power switches for DVS is less well understood. This paper characterizes power switches for DVS in terms of VDD-switching delay and VDD-switching energy. We show the impact of these switching overheads on a novel fine-grained DVS architecture and present an RC model that allows fast estimation of the overhead. Measurements of a DVS multiplier and adder on a 90 nm CMOS test chip validate the model. Our model and measurements confirm that power switched DVS can provide sufficiently low overhead to give energy savings with only one clock cycle spent at a lower voltage, making this approach a flexible and enticing option for embedded portable systems.

Over the past decade, process parameter variations have been one of the key design challenges. At circuit level of abstraction, process parameter variations cause deviation in the design specifications which threaten the parametric yield, resulting cost implication on the semiconductor industry. Post-silicon tuning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) are the most commonly used techniques to mitigate the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we first examine the effect of process parameter variations on parametric yield loss. Further, we propose a framework that integrates ABB and DVS techniques to effectively mitigate the impacts of process parameter variations even for sub-45nm CMOS technology. We test the proposed approach w.r.t. Hybrid Redundant Multiply-and-Accumulate (HR-MAC) unit, however the proposed approach can be utilized for any digital circuit.

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.KeywordsExecution TimeSupply VoltageKnapsack ProblemBasic BlockProgram RegionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Scaling of CMOS technologies below 20nm and supply voltages under 1V intensifies the need of low voltage ESD protection. Conventional ESD diodes requires higher breakdown voltage (>>1V) to trigger Avalanche or Zener tunneling mechanism. Recently, symmetric NIPIN structure was shown having low breakdown voltage utilizing the sub-bandgap impact ionization for bi-directional ESD protection. Here, NIPIN strcuture with designbale asymmetry is demonstrated for low voltage unidirectional ESD protection. Further, a reduction in capacitance is demonstrated which is needed for high speed interfaces. The designed NIPIN diode achieves ∼25% less capacitance than symmetric diode with V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf>∼0.66V. The design provides an efficient, scalable solution for protecting high-speed, low-voltage I/O interfaces for system level ESD protection.

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.

Summary form only given. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include power gating, power gating with retention, multiple supply voltages, dynamic voltage scaling, adaptive voltage scaling, multi-threshold CMOS, and active body bias. The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created. We look into verification issues along with the solutions to these issues using a verification strategy that involves power-aware simulation, rule-based structural checking, formal tools, and methodology recommendations. We detail our varied experiences with various design teams in addressing these low power verification issues for applications such as the wireless handset, low power microprocessors, and GPS.

This paper presents a dynamic voltage scaling (DVS) compatible single-inductor multiple-output (SIMO) voltage regulation module that enables smaller passives for a given output power, while maintaining power quality (low output ripple), suppressing cross regulation, and improving efficiency at high switching frequency. First, continuous-conduction mode (CCM) operation is utilized to deliver higher output power for a smaller inductance; the cross-regulation in CCM operation is suppressed using a novel power-weighted CCM controller. Second, a modified power stage filter is presented using floating capacitors that utilize the Miller effect to reduce the switching frequency of the output, while maintaining the power quality. The operating principles, stability, and circuit level design of the proposed SIMO VR are presented. The design is demonstrated through a 130-nm CMOS test chip that generates four outputs, each ranging from 200 to 600 mV, from a 1.2-V input. The measurements demonstrate a 20-MHz operation, the pulse width modulation signal of the power stage with 500-nH inductor, and 1-μF total load capacitance, while delivering a output power density of 150 mW/μH·μF. The test chip demonstrates DVS speed of 120 mV/μs, 73% peak efficiency at a load of 40 mA, and as high as 40% efficiency improvement using the modified power filer.

Reduction of power dissipations in CMOS circuits needs to be addressed for portable battery devices. Selection of appropriate transistor library to minimise leakage current, implementation of low power design architectures, power management implementation, and the choice of chip packaging, all have impact on power dissipation and are important considerations in design and implementation of integrated circuits for low power applications. Energy-efficient architecture is highly desirable for battery operated systems, which operates in a wide variation of operating scenarios. Energy-efficient design aims to reconfigure its own architectures to scale down energy consumption depending upon the throughput and quality requirement. An energy efficient system should be able to decide its minimum power requirements by dynamically scaling its own operating frequency, supply voltage or the threshold voltage according to a variety of operating scenarios. The increasing product demand for application specific integrated circuit or processor for independent portable devices has influenced designers to implement dedicated processors with ultra low power requirements. One of these dedicated processors is a Fast Fourier Transform (FFT) processor, which is widely used in signal processing for numerous applications such as, wireless telecommunication and biomedical applications where the demand for extended battery life is extremely high. This paper presents the design and performance analysis of a low power shared memory FFT processor incorporating dynamic voltage scaling. Dynamic voltage scaling enables power supply scaling into various supply voltage levels. The concept behind the proposed solution is that if the speed of the main logic core can be adjusted according to input load or amount of processor's computation "just enough" to meet the requirement. The design was implemented using 0.12 &#956;m ST-Microelectronic 6-metal layer CMOS dual- process technology in Cadence Analogue Environment.