Scaleable retrograde p-well CMOS technology

The formation of high-resistivity regions in Si-doped (n=1×1018 cm−3) lattice-matched In0.75Ga0.25As0.54P0.46 on InP by nitrogen and boron ion irradiations at 300 K, and by helium ion bombardment at 80, 300, and 523 K has been investigated as function of ion dose (1×1012–1×1016 cm−2) and subsequent anneal temperature (70–650 °C) by sheet resistance and Hall effect measurements. The dose dependence of the sheet resistance shows two regions for all cases considered: (I) for lower doses in which the sheet resistance (resistivity) increases up to a maximum of about 6×106 Ω/⧠ (180 Ω cm), and (II) for higher doses in which the sheet resistance decreases with dose. Temperature dependent Hall measurements for materials in region (I) show thermally activated carrier densities with activation energies between 0.21 and 0.29 eV. The temperature dependence of the sheet resistance in region (II), on the other hand, is consistent with the assumption of a hopping conductivity. Varying the substrate temperature during the irradiations yields no measurable effects for samples implanted in region (I). For the case of He+ bombardments at 523 K, higher sheet resistances are obtained in region (II) as compared to samples irradiated at lower temperatures. For the case of He+ at 80 K and N+ at 300 K a third region (III) is observed for doses higher than 7 and 2×1014 cm−2, respectively, in which a renewed increase in the sheet resistance with increasing dose is detected. Rutherford backscattering-channeling results suggest that this behavior is related to the creation of an amorphouslike region in the InGaAsP layer. Annealing of samples amorphized by He+ at 80 K yields higher resistivities (up to a factor of 6×105 relative to that of the unimplanted material), and improved stability of the high resistivity as compared to the other implantation schedules investigated.

We have investigated the limits on sheet resistance, junction depth and abruptness using ultra low energy As implants and RTA annealing. We report on anomalous diffusion of 1 keV arsenic implants where the same RTA anneal can result in a deeper junction compared to a 5 keV implant of similar dose. A range of anneal times and temperatures in an RTA from 1020C to 1175C, including spike anneals, have been studied. The effect of junction abruptness in reducing the external resistance of the S/D extension for these 5 and 1 keV As implants has been investigated. We show that because of a trade off between junction depth and sheet resistance limits, 1 keV As implants and RTA anneals cannot meet the technology roadmap requirements beyond 2005, though the junction abruptness will meet the requirements till 2011.

P was diffused into p-type Si wafers containing B at 1100/spl deg/C for six different times using a solid state source and a standard pre-deposition process. Secondary ion mass spectrometry (SIMS) provided profiles of dopant concentration versus wafer depth from which both the surface concentration and the junction depths for the six wafers were determined. These profiles were fitted acceptably well by the constant supply model of diffusion in the dilute tail region identified by Fair, although indications of concentration-dependent diffusion were observed. Two independent determinations of the sheet resistivity of each sample were made. The results confirmed the correct operation of our custom-built sheet resistivity system. The resulting data allow us to predict the junction depth within 0.2 /spl mu/m over a range from 1.0 to 2.0 /spl mu/m. A plot of the dopant surface concentration, N/sub 0/, versus the product of the sheet resistivity and the junction depth, R/sub s/x/sub j/, agrees well with data from the Irvin plot.

According to the recently released 1999 National Technology Roadmap for Semiconductors, the SID extension junction will be in the range of a few tens of nanometers for the up coming 180 nm and 130 nm nodes. Although the junctions have to become shallower, a decreasing sheet resistance is required. The formation of ultra-shallow junctions is mainly influenced by three important parameters, these are: dose and energy control during ion implantation, a controlled gaseous ambient during RTA (rapid thermal anneal), and a controlled and reproducible thermal budget during RTA. The requirements for production tools have become progressively more stringent, but the crystal off-orientation of the wafer surface condition as an issue in reproducible USJ formation has been neglected. In Si wafer production, the exact [100] orientation of the wafer surface is determined by the ingot sawing accuracy and typically done with a tolerance of +0.1/spl deg/. Prior to this experiment, however, the influence of such a variance in the wafer off-orientations on the junction characteristics had not been investigated. For our experiments repeatable "off-axis" from [100] sliced 200 mm silicon wafers were implanted with /sup 11/B/sup +/, /sup 75/As/sup +/ or /sup 31/P/sup +/ at a tilt and twist angle of 0/spl deg/ to investigate the effects on junction depth and sheet resistance. The acceleration voltage varied between 500 eV (/sup 11/B/sup +/) and 5 keV (/sup 75/As/sup +/). The off-orientation varied between exact 0/spl deg/ and the channeling-reduction-angle for boron of 7.00 (e.g. 0.35/spl deg/, 1.0/spl deg/, 4.0/spl deg/). Species depending data of as-implanted distributions as well as soak time (1050/spl deg/C 10 s) and flash annealed (with a ramp rate of 350 Ws) wafers are presented and the influences of the off-oriented sliced wafers on junction depth and sheet resistance are discussed.

Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi 2 /n+-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr 3 at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. Transistor I-V 's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p+regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n+and p+junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.

Self-healing behaviors of metallized high-temperature dielectric films for capacitor applications

and nitrogen-doped films were deposited by dc magnetron sputtering on substrates and the effects of antimony (Sb) and nitrogen (N) doping on microstructure and sheet resistance were investigated. After annealing at various temperatures between 100 and , phase transformations in and nitrogen-doped films were investigated using X-ray diffraction (XRD) and transmission electron microscopy (TEM). The sheet resistance of those samples was measured by four-point probe. XRD and plan-view TEM analysis showed that the addition of Sb and N elements to pseudo-binary caused crystallization and phase transformation from face-centered cubic (fcc) structure to hexagonal close-packed (hcp) structure to occur at higher temperatures with grain refinement. Also, the Sb and N doping produces increased sheet resistance in films with improved phase stability of amorphous and fcc structures up to higher temperatures. N-doped with high sheet resistance is favored for phase-change random access memory application because of reduced writing current with increased crystallization speed and thermal stability.

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors using major process parameters such as dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration is described. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.

A systematic and general method of computing ac and dc characteristics of double-diffused junction transistors is described using major process parameters such as: dimensions of the device, surface concentration, junction depth, diffusion time, temperature, and diffusion coefficient as a function of temperature and impurity concentration. These parameters can be checked during the process and, therefore, can aid the process control problem by predicting the expected values of junction depth and sheet resistivity. If the specified control parameters are met during the fabrication, the ac and dc characteristics of the device will be realized. The time and/or frequency response of a circuit can be computed using the ac and dc characteristics of the diffused devices of the circuit on the basis of a distributed or an equivalent lumped model. The measurement of important ac parameters on the basis of these models has also been simulated on the computer, thus aiding the characterization problem of the device in the integrated circuit environment. Also, the switching speed of a loaded logic net can be computed and optimized by trading off interacting parameters and relating them back to the original diffusion process parameters and dimensions of the components. Finally, experimental verification of the computed results has been accomplished and found to be satisfactory.

Negative capacitance field-effect transistor (NCFET) is one of the very promising emerging technologies that may replace existing CMOS technology in the future. This is due to its ability to push the sub-threshold swing of transistors to below 60 mV/decade, which what fundamentally limits voltage scaling in conventional CMOS technology and what has led in the past to the discontinuation of Dennard’s scaling. In this chapter, we demonstrate how NCFET technology can reshape the future of many-core systems—especially when it comes to thermally constrained processors. Compared to conventional CMOS technology, NCFET technology allows processors (1) to be clocked at higher frequency without any increase in the power density or (2) to operate at lower voltages, without sacrificing performance requirements. The latter leads to a significant power saving that plays a major role in increasing the total number of processor cores that can be simultaneously powered on without exceeding the predetermined thermal constraints. In addition, we demonstrate how NCFET technology makes the leakage power in processors increase, instead of decrease as in conventional CMOS technology, when voltage is scaled down. This fundamentally breaks down the core assumption of all existing power management techniques. Hence, novel runtime power management techniques need to be devolved in which such a new inverse leakage-voltage dependency is carefully considered. Otherwise, the efficiency of NCFET-based processors cannot be optimized. In this chapter, we also demonstrate the first NCFET-aware dynamic voltage scaling that optimizes the power of processor while taking the inverse leakage-voltage dependency into account.KeywordsMany coresEnforcementNon-functional requirementsReal-timeCentralizedDistributed

A multienergy oxygen ion implantation process was demonstrated to be compatible with the processing of high-power microwave AlGaN/GaN high electron mobility transistors (HEMTs). A high sheet resistivity and thermally stable isolation were demonstrated. The microstructures of implanted and postannealed specimens were investigated by transmission electron microscopy (TEM). The dependences of the sheet resistivity and different postannealing temperatures were correlated with the defect clusters and microstructure of lattice stacking faults. After 300 °C annealing, the sheet resistivity was higher than 1012 Ω/square, which was attributed to the severe defect interaction eliminating the trapping centers and reducing the leakage current. A maximum output power density of 5.3 W/mm at Vgs=-4 V and Vds=50 V at 3 GHz was demonstrated on lag-free HEMTs without field plates on sapphire substrate.

Optimal Control of Transient Enhanced Diffusion

As the size of CMOS devices continues to scale down, the reliability of circuits becomes one of main challenges in low supply voltage designs. Markov Random Field (MRF) circuits, a probabilistic-based approach, can achieve higher noise immunity compared to traditional designs under conditions of ultra-low supply voltage and low threshold voltage. However, the basic MRF elements have complex structures and become a stringent factor that limits MRF-based VLSI design. In this paper, we provide a partial-clique-energy MRF (PMRF) design method, trading off the noise immunity for area efficiency. We then propose an Enhanced PMRF (EPMRF)-pair for multi-level and multi-function joint PMRF designs. The main idea is to use the joint clique energy of two complementary partial clique energies to make up performance losses. The measurement results show that, the proposed EPMRF pair can operate at 0.25 V with 10−4 dB output noise power with 5.6 dB input signal-noise ratio (SNR). With the 130 nm CMOS technology, the chip of our EPMRF based carry-look-ahead adder achieves 29% area-saving and 55% energy-saving compared to existing ultra-low supply voltage fault tolerant designs.

As CMOS technology has a scaling limitation in deep nanometer technologies, the best alternative for CMOS technology is a Quantum - Dot Cellular Automata (QCA) technology. Quantum dot Cellular Automata has the combined nature of both quantum mechanics and cellular automata. The QCA technology has many advantages than transistor based technology such as small size, high speed, and low power consumption. The working principle of QCA technology is at the molecular level. In conventional CMOS technology, transistors are used to create a logic gate. But in QCA technology, QCA cells are used to create logic gates and wire. The basic logic elements are an inverter and the majority gate. By using these elements many of the combinational and sequential circuits are created. In this brief, we propose the binary up counter using T flip flop. 2 bit and 3 bit Counters are implemented using the above mentioned QCA technology. The layout was designed and the functionality of the counter circuit was verified using QCADesigner tool.