Polysilicon gate depletion effect on deep-submicron circuit performance

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

This paper deals with MOS transistors mismatch for advanced 120 nm and 90 nm CMOS technologies. In particular we demonstrate pocket implant impact on the gate contribution that becomes more and more important with the gate oxide thickness reduction. Such a phenomenon can appear as a limit for matching improvement with CMOS technologies evolution.

Integration of process, device and circuit simulation tools is desirable in modern process development and circuit design, as it allows rapid assessment of the impact of a new process or process change on circuit performance, [1]. This paper presents an efficient scheme for the extraction of MOSFET linear region SPICE level 3 parameters from numerical device simulations. Carrier concentrations, potential and mobility are used to derive a total of seven linear region parameters from three off-state bias points. This is in contrast to standard curve fitting techniques where twenty or, more on-state bias points would typically be used to obtain the required parameters.

In this paper, we study the band structures of Si and InAs nanowires based on a first-principles calculation and project performance potentials of Si and InAs nanowire field-effect-transistors (NWFETs) by using a semiclassical ballistic transport model. We demonstrate that the device performance of InAs NWFETs strongly depends on its cross-sectional dimension and gate oxide thickness. In particular, InAs NWFETs unexpectedly indicate lower current drivability than Si NWFETs as the gate oxide thickness is extremely scaled down to 0.5 nm in the ballistic limit. We discuss the mechanism in terms of operation in quantum capacitance limit (QCL). We also demonstrate that the advantage in the lower power operation with InAs NWFETs reduces when the devices operate in the QCL or higher subbands with a heavier transport effective mass participate in the transport.

The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.

We correlated the off-state current in polycrystalline silicon (polysilicon) thin film transistor (TFT) with the peak electric field in the channel of the device. We investigated p-channel TFTs with different gate oxide thicknesses, at varying gate and drain biases. The electric fields in the channel of the devices under these experimental conditions were calculated using both process and device simulators, and the experimental off-state current was plotted against simulated fields. We found that in a wide range of electric fields the current exhibits a nearly exponential behavior. Different combinations of the drain and gate biases produce nearly the same off-state current, provided the calculated peak field is the same; moreover, curves corresponding to different gate oxide thicknesses overlay each other. Our results are compatible with the model of the off-state current as being due to the field emission at grain boundaries.

Semiconductor nanowire transistors are considered potential successors of finFETs providing the ultimate miniaturization capabilities of MOS transistors and thus targeting ultimate circuit complexity and performance. A promising perspective for further advancement beyond classical CMOS scaling is to exploit functionality enhancement of nanowire transistors. Several nanowire based multi-gated device concepts known as reconfigurable field effect transistors (RFETs) or polarity control FETs that combine multi-functionality with the inherent advantages of silicon nanowires are being currently evaluated [1-4]. These multi-terminal devices merge unipolar n- and p- FET switching characteristics from the same device as selected simply by an electric signal and without the need for doping enabling complementary CMOS operation with a single kind of transistor. RFETs make use of two sharp metal-NiSi2 / intrinsic-silicon interfaces with individual gates for the selective injection of electrons and holes into the channel region [5]. Additional independent steering gates can be integrated to further enhance functionality without comprising on-conductance [6]. In order to allow complementary circuit operation symmetry in the p- and n-type I-Vcharacteristics is mandatory. To this end, we show both experimentally [7] and by device simulations [8] that the application of radial compressive strain to <110> oriented silicon nanowires is able to align the injection efficiency of electrons and holes for diverse nanowire geometries. Full swing complementary operating circuits such as inverters [7] and compact six transistor cells yielding NAND, NOR and minority functions as demonstrated with symmetric RFETs and 3XOR gates with only 8 transistors vs. 24 with CMOS [6,7,10,11]. These gates build the basis for arithmetic building blocks such as one-bit adders with substantially lower transistor count reducing critical pathes, delay and power consumption as compared to conventional CMOS [6]. The RFET concept has been recently successfully transferred to a parallel nanowire technology [12,13] principally enabling to build low operation power circuits and sensors on plastic substrates. Finally, we show that germanium based RFETs improve the individual device performance and to reduce dynamic power consumption without comprising static power consumption. Figure caption: a) Schematic of reconfigurable nanowire FET (RFET) encompassing intrinsic Si nanowire channel and two independently gated Si / NiSi2 junctions. b) Oxide induced compressive stress in Si nanowire core required to adjust electron and hole currents: TEM cross section of nanowire channel with overlay of computed mechanical strain distribution. c) SEM image of abrupt Si / NiSi2 junction. d) SEM of symmetrically operating RFET with electrical device symbol. e) Symmetric p- and n-program I-V transfer characteristics of device depicted in d). f) SEM of inverter built of two RFETs within a single nanowire. g) Measured inverter transfer characteristic with supply voltage of Vdd = 2V showing low operation power complementary behavior and full swing output. Propagation delay for scaled structure and for different fanouts. Output of reconfigrable NAND/NOR/Minority 6-transistor cell, shows reconfiguration at runtime (mixed -mode computations). h) High-yield printed silicon nanowire FETs encompassing ~ 1xE3 parallel nanowires with meander source/ drain / gate structure. Technology is compatible with flexible plastic substrates.

Process modeling is widely used in the design of both integrated circuits themselves and in the design of integrated circuit manufacturing processes. Director1 gives an overview of the roles of process, device, and circuit simulators in the overall design process. Process simulation has been used for many years for more mature processes such as oxidation, diffusion, and ion implantation, and the widely used computer simulation programs for these processes use physically based, first principles models.2,3 Simulation is also widely used to predict the performance of resist development, etching, and film deposition processes.4,5 However, the process simulation models which are currently used to predict the performance of these processes are not first principles models. The current generation of plasma etching and deposition models is based on heuristic rules which describe the propagation of a moving boundary rather than on the solution of the fundamental equations which describe the underlying, physical processes. In fact, the required input data for current plasma etching and deposition models are experimentally measured etch and/or deposition rate values.

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

From the Publisher: This book presents for the first time a unified treatment of the physical processes, mathematical models and numerical techniques for circuit, device and process simulation. At the macroscopic level, linear and nonlinear circuit elements are introduced to yield a mathematical model of an integrated circuit. Numerical techniques used to solve this coupled system of one-dimensional equations are described. Microscopically, current flow within a transistor is modeled using the drift-diffusion and hydrodynamic partial differential equations systems. Finite difference and finite element methods for spatial discretizations are treated, as are grid generation and refinement and multilevel schemes. At the fabrication level, physical processes such as diffusion, oxidation and crystal growth are modeled using reaction, diffusion, convection equations. These models require multistep integration techniques and Krylov projection methods for successful implementation. Exercises, programming assignments and an extensive bibliography are included.

The main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models for a developing deep sub-micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. The ability to estimate the worst-case SPICE models for a process, based on the physical variations of process parameters, is critical for the prediction of statistical circuit performance variabilities. Silvaco's line of simulation products enables process engineers to predict the effects of process changes on device performances. Changes in process parameters and mask variation are described using the Virtual Wafer Fab (VWF) framework. The ATHENA process simulator, the ATLAS device simulator and the UTMOST parameter extractor are included in this framework. The SPICE models extracted by UTMOST as part of a VWF experiment may be imported into SPAYN for a detailed statistical analysis and model parameter sets corresponding to various process corner are derived. SPAYN, in turn, can be linked to our circuit simulator SMARTSPICE. This allow circuit performance to be analyzed using the corner models so that worst-case circuit performance for any particular circuit application can be identified. Monte Carlo or user defined circuit simulations, using correlated parameter sets arising from the analysis of the extracted parameters (Principal Component Analysis for example), are also run directly from SPAYN.

PurposeThe high computational effort of steady-state simulations limits the optimization of electrical machines. Stationary solvers calculate a fast but less accurate approximation without eddy-currents and hysteresis losses. The harmonic balance approach is known for efficient and accurate simulations of magnetic devices in the frequency domain. But it lacks an efficient method for the motion of the geometry.Design/methodology/approachThe high computational effort of steady-state simulations limits the optimization of electrical machines. Stationary solvers calculate a fast but less accurate approximation without eddy-currents and hysteresis losses. The harmonic balance approach is known for efficient and accurate simulations of magnetic devices in the frequency domain. But it lacks an efficient method for the motion of the geometry.FindingsThe three-phase symmetry reduces the simulated geometry to the sixth part of one pole. The motion transforms to a frequency offset in the angular Fourier series decomposition. The calculation overhead of the Fourier integrals is negligible. The air impedance approximation increases the accuracy and yields a convergence speed of three iterations per decade.Research limitations/implicationsOnly linear materials and two-dimensional geometries are shown for clearness. Researchers are encouraged to adopt recent harmonic balance findings and to evaluate the performance and accuracy of both formulations for larger applications.Practical implicationsThis method offers fast-frequency domain simulations in the optimization process of rotating machines and so an efficient way to treat time-dependent effects such as eddy-currents or voltage-driven coils.Originality/valueThis paper proposes a new, efficient and accurate method to simulate a rotating machine in the frequency domain.

In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.

This paper describes a three-dimensional device simulator, TOPMOST, and its use in the analysis of the anomalous subthreshold current "hump" in a fully recessed oxide MOS structure. TOPMOST solves Poisson's and current continuity equations using the finite-difference method and the box-integration technique, which has been extended to suit an arbitrary three-dimensional structure. The device simulator can be optionally coupled with a two-dimensional process simulator for investigating the influence of process conditions on device performances. Using TOPMOST, the subthreshold current characteristics of a fully recessed oxide structure are examined. The mechanism underlying the hump is clarified, and the dependence on structure parameters, such as channel width, gate oxide thickness, and gate extension, are studied. It is shown that there is a worst case where the current hump becomes most conspicuous. It is also shown that the hump can be suppressed by a side-wall implantation.

The dynamic switching characteristics of high-power GaAs Schottky and silicon p-i-n rectifiers are studied at various temperatures. Devices were first characterized to measure forward and reverse I-V, C-V, reverse breakdown voltage, and reverse-recovery performance. The same devices were characterized for turn on and turn off in switching circuits designed to study the dynamic switching performances under hard- and soft-switching conditions at different temperatures. Advanced two-dimensional (2-D) mixed device and circuit simulations were used to study the internal plasma dynamics under boundary conditions imposed by the circuit operation. It is shown that for hard-switching applications, GaAs Schottky power rectifiers exhibit significantly reduced switching power losses compared to silicon p-i-n rectifiers. For soft-switching applications, there is not a significant difference in the switching power losses for these two devices. Diode performance at elevated temperatures is measured and simulated, and temperature dependencies of switching and conduction power losses are analyzed.