Circuit, device and process simulation: mathematical and numerical aspects

The paper presents the research of the numerical simulation techniques and the preliminary experimental validation on the start characteristics for a typical two-dimensional (2D) hypersonic inlet. In order to obtain the start and unstart hysteresis loop, numerical simulations methods using the incoming flow field, the zero-velocity flow field, and the latest convergent flow field as the initialized flow field separately are adopted to calculate the inlet start characteristics until the flow fields converge. The calculation software is AHL3D, a parallel computational fluid software self-developed by CARDC. The numerical methods also include the method from unstart flow field to start one with Mach-numbers gradually increasing till the inlet is start and the method from start flow field to unstart one with Mach-numbers decreasing till the inlet is unstart. According to the comparison with different initialized flow field and with different step-size of Mach-number, the inlet start characteristics are obtained and the numerical techniques are analyzed. Based on the comparison and the analysis, it is suggested that the numerical techniques of inlet start characteristics should use the zero-initialized flow field with one step to the final Mach-numbers to predict the minimal self-start Mach-number of the inlet and use the incoming flow-initialized flow field to predict the minimum start Mach-number. The results show that the numerical techniques are high-efficient and easily operational. To verify the effect of the numerical techniques, wind tunnel tests are arranged to research the start characteristics of a typical 2D hypersonic inlet. The preliminary experimental result shows that the numerical techniques of predicting inlet start characteristics are consistent with the experiments very well, which means that the application of the numerical techniques can be further carried out for such hypersonic inlets as mentioned in the current paper.

Process modeling is widely used in the design of both integrated circuits themselves and in the design of integrated circuit manufacturing processes. Director1 gives an overview of the roles of process, device, and circuit simulators in the overall design process. Process simulation has been used for many years for more mature processes such as oxidation, diffusion, and ion implantation, and the widely used computer simulation programs for these processes use physically based, first principles models.2,3 Simulation is also widely used to predict the performance of resist development, etching, and film deposition processes.4,5 However, the process simulation models which are currently used to predict the performance of these processes are not first principles models. The current generation of plasma etching and deposition models is based on heuristic rules which describe the propagation of a moving boundary rather than on the solution of the fundamental equations which describe the underlying, physical processes. In fact, the required input data for current plasma etching and deposition models are experimentally measured etch and/or deposition rate values.

A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.

New Topics in Simulation and Modeling of RF Circuits addresses two main topics: simulation of RF circuits and new models of nonlinear power BAW resonators and filters.Since RF circuits have several unique features, and all analysis methods are based on the circuit essential properties, the book begins by describing the properties of RF circuits, characterization of circuits with customary and uncustomary behavior and some theorems of solutions existence and uniqueness for dynamic nonlinear circuits. Thereafter, the main time domain and frequency domain analysis methods for RF circuits are presented. The advantages and disadvantages of each method have been highlighted, and an algorithm for the time step choice in transient analysis based on energy balance errors is also presented. Lastly, the final part contains some nonlinear circuit models of power BAW resonators. The behavioral models for the time domain analysis are simple circuits containing weakly nonlinear elements. The behavioral models for frequency domain analysis are based on the measured values of the frequency dependent S parameters for a set of incident powers. S parameters corresponding to certain intermodulation products of practical interest are also considered. The physical models contain artificial transmission lines with nonlinear circuit elements corresponding to mechanical and electrical nonlinearities.

Integration of process, device and circuit simulation tools is desirable in modern process development and circuit design, as it allows rapid assessment of the impact of a new process or process change on circuit performance, [1]. This paper presents an efficient scheme for the extraction of MOSFET linear region SPICE level 3 parameters from numerical device simulations. Carrier concentrations, potential and mobility are used to derive a total of seven linear region parameters from three off-state bias points. This is in contrast to standard curve fitting techniques where twenty or, more on-state bias points would typically be used to obtain the required parameters.

A two-dimensional (2-D) physical model of n-channel poly-Si LDD TFTs in comparison with that of SD TFTs is presented to analyze hot-carrier degradation. The model is based on 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. We have shown that, in the current saturation bias (Vg < V d ) in LDD TFT, the maximum 2-D lateral electric field is in the deep region under the gate edge, and the current flows in the deep channel region near the drain junction. These results suggest that the drain avalanche hot-carrier (DAHC) degradation first occurs at both the gate oxide/poly-Si and polySi/substrate interfaces and grain boundaries in deep LDD region under the gate edge due to the state generation. In the weak current saturation bias (V g =V d ), weak channel pinch-off occurs near the channel/LDD junction and degradation due to hot-electron injection into the gate oxide under the gate will occur in the LDD region.

This paper describes advances and remaining challenges in unstructured 3D meshing techniques for both process and device simulations and parallelization of the process simulator FLOOPS. The meshing is performed using a point cloud manager to create points and an unstructured tetrahedral mesher. Distributed parallel techniques are used to parallelize the sparse matrix assembly and solution for 3D process diffusion simulations.

To develop and optimize semiconductor devices it is common practice to advocate numerical device modeling by using simulation programs. Typically the simulation of a unit is split into levels, starting with process simulation (to study the effect of wafer-processing steps) and device simulation (to study the electrical behavior), to circuit simulation (to study the electrical features of an ensemble of devices), leading possibly to the logic simulation of a whole unit. Unfortunately, this approach makes it very hard to model the interaction of the device and the circuit in the transient case: therefore, in order to optimize the transient behavior of a particular device it is necessary to include the effects of both the drive circuit (i.e., control part), as well as the load circuit. During the last year, we have developed a software environment for combined device-circuit simulation studies dedicated to semiconductor power devices, magnetic field sensors, and Bicmos structures augmented with simple circuits. In our work we discuss some critical points in detail. These include the grid generation and adaptation, the scaling of the unknowns (i.e., how to deal with high voltages), the numerical procedures used to solve the transient problem (with special attention to supercomputer architectures), the assembly of the device (element assembly versus edge assembly) and circuit equations as well as the physical models used. We show that it is essential to properly chose the numerical techniques to obtain accurate and reliable results. Studies of the turn-off of power devices, the switching of BiCMOS structures, and of magnetic field sensors indicate the success of the current approach.

Improving the fatigue performance of porous metallic biomaterials produced by Selective Laser Melting

Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.

Industry-standard TCAD software packages are widely used by semiconductor companies to optimise processes and devices in integrated circuits fabrication. After process and device simulation one can go ahead with circuit simulation using Spice. This paper focuses on the matching of these program packages in the area of parameter and characteristics extraction. We compared the transfer characteristics of n-type MOSFET, biased in the linear region, obtained from Synopsys package including TSUPREM4 and MEDICI with transfer characteristics from PSpice package.

This volume contains the proceedings of the 10th edition of the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2004), held in Munich, Germany, on September 2-4, 2004. The conference program included 7 invited plenary lectures and 82 contributed papers for oral or poster presentation, which were carefully selected out of a total of 151 abstracts submitted from 14 countries around the world. Like the previous meetings, SISPAD 2004 provided a world-wide forum for the presentation and discussion of recent advances and developments in the theoretical description, physical modeling and numerical simulation and analysis of semiconductor fabrication processes, device operation and system performance. The variety of topics covered by the conference contributions reflects the physical effects and technological problems encountered in consequence of the progressively shrinking device dimensions and the ever-growing complexity in device technology.

A standard format for transmitting profiles of semiconductor structures between sites and between tools is described. The standard, called the profile interchange format (PIF), is a flexible and hierarchical format, capable of storing descriptions of semiconductor structures such as those produced and used by process and device simulators. It can store detailed descriptions of the geometry, attribute profiles, material properties, and transient behavior of a single structure or a collection of structures. Two equivalent forms of the PIF are proposed to resolve conflicting demands placed on the format by its two primary uses, which are transmitting profiles between sites and local use as a database for process and device simulation. The 'intersite' form of the PIF, which can be viewed as an extension of the electronic design interchange between sites, most importantly, portability. The 'intertool' form of the PIF is, in concept, equivalent in descriptive capabilities to the intersite form, but is intended to accommodate the needs of profile interchange between tools, most importantly, efficient storage and access of data. The PIF in both modes can be extended and modified to accommodate local needs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

To seek an earth-abundant and environmentally friendly absorber for thin-film solar cells, Cu3PSe4 is investigated by first-principles calculations and device simulations. We demonstrate that the compound has a suitable band gap width of 1.3 eV as well as a high sunlight absorption coefficient. However, drawbacks like small electron affinity, high hole concentration, large lattice mismatch with CdS, etc., are revealed, which may degrade the photovoltaic performance. To address those shortcomings, we propose (1) to optimize the carrier concentration by preparing the samples at low temperature and under a Cu-rich environment, (2) to replace the CdS buffer layer by a more suitable wide-gap semiconductor with smaller lattice mismatch, and (3) that the selected buffer layer should have small electron affinity in order to reduce the open-circuit voltage losses. After implementation of these optimization approaches, the device simulations demonstrate that the power conversion efficiency reaches 17.7% for a solar cell with the configuration Mo/Cu3PSe4/WS2/n-ZnO. The combination of first-principles calculations at the atomistic level and device simulations at the macroscopic level provides an appropriate approach to design ideal solar cells.

By integrating the efforts in process, device and circuit simulations, this paper investigates the polysilicon-gate depletion effect (PDE) on performance of circuits composed of deep-submicron transistors. The DC and AC components of PDE on circuit performance are separated for the first time. The study delineates quantitatively the competing effect between the DC and AC PDE. Results of this study suggest the following: (i) PDE degrades circuit speed through dominance of the DC component in the competing effect. Reduction of gate oxide thickness lessens this DC PDE dominance behavior. (ii) Circuit speed degradation due to PDE becomes more significant during low-power operation. (iii) The above phenomenon in (ii) can be substantially improved by thinning the gate oxide thickness. >