A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture

Direct digital frequency synthesis (DDS) as an indispensable key technology for modern communication systems, is widely used in digital communications, satellite communications, aerospace and high-speed instrumentation. In practical applications, DDS technology is usually required to generate different kinds of communication signals. In view of the fact that there is no related research on spurious signals when DDS technology generates communication signals, this paper based on a DDS model that can generate arbitrary symbol rate communication signals, analyzes spurious signals of the structure in detail. The conclusions of this paper can be used for the spur evaluation and parameter selection in DDS engineering applications. At the same time, this paper provides a theoretical basis for the low spurious design of DDS, and has certain reference value for DDS to generate communication signals.

This work presents a low power direct digital frequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier. A synthesized 0.35-mu DDFS with a SFDR of -80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-mW/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS

This paper presents an ultra-high-speed direct digital frequency synthesizer (DDS) microwave monolithic integrated circuit (MMIC) implemented in 1μm GaAs HBT technology. The DDS has the capabilities of direct frequency modulations with 8-bit frequency resolutions. Utilizing a Double-Edge-Trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC based ROM-less architecture, this DDS MMIC can maximize the utilization ratio of GaAs HBT's high-speed potential. With an external clock output frequency of 5GHz, the DDS can output sine signal of up to 5GHz frequency giving an average Spurious Free Dynamic Range (SFDR) of 23.24dBc through the first Nyquist band. The DDS MMIC consumes 2.4W of DC power from a single -4.6V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 × 2.0mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An experimental platform was developed to investigate the effects of audible sound (20 Hz to 20 MHz) on plant growth promotion, which included a microcontroller-based embedded system for audible sound adjustment and analysis. The direct digital frequency synthesis (DDFS) method was used to generate various waveforms of sound in the platform. Soundproof glass and mufflers were used to reduce background noise. The developed system was tested on various plants, including hydroponic tomatoes, celery and mung bean. The testing results showed that the developed platform could produce pure tone and mixing audible sound with high stability and accuracy, make octave analysis of the sound under experimental environments, and the background noise in the testing chamber of the platform was lower than 55 dB(A) when the compression engine was working. The developed experimental platform has a great potential on facilitating scientific research on acoustic biology effects on plants and collecting real-time experimental data. Keywords: plant growth, background noise, acoustic biology effect, direct digital frequency synthesis, sound sensor DOI: 10.3965/j.ijabe.20150805.1556 Citation: Cai W M, Zhu S M, Wang N, He H N, Ying B H. Design of an experimental platform to investigate the effects of audible sounds on plant growth. Int J Agric & Biol Eng, 2015; 8(5): 162－169.

Direct Digital Frequency Synthesizer (DDFS) has long been perceived as a predominant solution for producing precise, variable frequency signals having very low distortion. The paper presents an epigrammatic and a comparative study of direct digital frequency synthesizers architectures. The direct digital frequency synthesizer presented are compared on the basis of two architectures namely, the read only memory (ROM) or look up table based architecture and the other co-ordinate rotation based digital computer that eliminates the usage of the large ROM based look up table. These architectures are compared in terms of the power utilization, SFDR, etc. A mixed signal ASIC designing approach is followed for the implementation approach.

In this paper, we analyze the design and the possible optimization methods of the direct digital frequency synthesizer (DDFS) based on quadratic approximation. The goal is to design a DDFS with reduced hardware cost and very high spectral purity. For the DDFS based on quadratic approximation, there is a trade-off between the size of the memory and the approximation logic. We show that by exploring this trade-off, it is possible to design a DDFS which requires less hardware and features higher spectral purity than the previously presented solutions. By using the proposed design method, a DDFS that generates 16-bit sinusoidal waves with a spurious free dynamic range of 132 dBc (126 dBc if the phase is truncated) was designed.

A ROM-less direct digital frequency synthesizer (DDFS) is implemented based on a new 8th-order polynomial approximation of a cosine function, where digital square circuits are used to realize the components of the polynomial. MATLAB tools are used to simulate the performance of the DDFS system, where the spurious free dynamic range (SFDR) is employed as the performance factor. For a DDFS with a superior quality, the higher the SFDR, the better the spectrum purity. To validate the performance of the DDFS, the Altera FPGA platform is used with Quartus II and ModelSim, where simulation results based on Verilog implementation are illustrated.

In order to test the working state of adaptive optics system, it is necessary to design an online sweep-frequency circuit module to test the frequency response of the adaptive system. Sweep-frequency signal generator based on Direct Digital frequency Synthesis (DDS) is one of the core components. But the classic DDS technology also has some drawbacks: the truncation error of phase, the truncation error of magnitude (caused by memory FWL) and high occupancy of ROM. These are also the optimization directions in this paper. This paper presents a FPGA-based DDS sweep-frequency signal generator suitable in adaptive optics. It has a low occupancy rate with ROM. And in the case of low-ROM, the paper reduces the noise generated by the truncation error of phase and the truncation error of magnitude of DDS sweepfrequency signal generator by method of linear interpolation. The results show that, when the reference frequency is 100 MHz, the frequency resolution can be as low as 0.025 Hz. It only takes up 0.5 KB ROM with the ROM compression ratio of 64:1 in the optimized scheme in the paper and has higher precision due to the method of linear interpolation than the unoptimized scheme, which can meet the engineering needs. Compared with other schemes, the scheme in the paper improves signal accuracy in the case of reducing the truncation error of phase, the truncation error of magnitude and the occupancy rate with ROM, but only adds a multiplication and division circuit, which is a practical solution.

In this paper, we propose an application of new direct digital frequency synthesizer, which clock frequency is up to 3.2 GHz. The design can generate single signal, chirp signal, stepped-frequency signal and stepped-frequency chirp signal from dc to 1500 MHz. The conclusions are drawn after comparing the NEW DDS with AD9858: phase noise and spurious spectrum of the NEW DDS are better than AD9858.

Spurious signals due to amplitude quantization in direct digital frequency synthesizers

Arbitrary Waveform Generator (AWG) is an important signal generation module in many applications such as communication and mixed signal testing. This paper describes an AWG based on Direct Digital Frequency Synthesizer (FFDS). The CORDIC algorithm with an iterative process and a pipeline plus parallel structure are used to implement the AWG whose frequencies and amplitudes of sinusoid waveforms in the arbitrary wave can be controlled by frequency control words (FCWs), initial vectors of CORDIC module respectively. Compared to the conventional AWG, it is flexible and saves much hardware.

Long Range(LoRa) Backscattering Communication (BC) not only has the advantages of low cost and low power consumption, but also has a long communication distance. However, the existing LoRa BC scheme is complex and can not be applied to actual engineering. For this purpose, a new LoRa BC method is proposed. A Direct Digital frequency Synthesis (DDS) technique is used to generate a square wave with a linear frequency variation as a LoRa scattering modulation signal. For the first time, the prototype of LoRa BC system based on MCU is demonstrated. Experimental results show that design can successfully realize backscatter communication at any position between the station and the receiver which are 208 meters apart, while being compatible with commodity LoRa chipset. In addition, the method is also applicable to an Application Specific Integrated Circuit (ASIC) design, which enables the LoRa backscattering IC to have higher robustness, lower cost, and lower power consumption.

This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multichannel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear DAC is implemented. The chip is fabricated in TSMC 130nm CMOS technology with active area of 0.89mm×0.98mm and total power consumption of 300mW at a single 1.2V supply voltage. The maximum operating speed is up to 2.0GHz at room temperature.

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.