基於八階多項式近似的ROM-less DDFS之FPGA實現

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.

A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The parabolic equations with proper selection of coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

This paper presents an ultra-high-speed direct digital frequency synthesizer (DDS) microwave monolithic integrated circuit (MMIC) implemented in 1μm GaAs HBT technology. The DDS has the capabilities of direct frequency modulations with 8-bit frequency resolutions. Utilizing a Double-Edge-Trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC based ROM-less architecture, this DDS MMIC can maximize the utilization ratio of GaAs HBT's high-speed potential. With an external clock output frequency of 5GHz, the DDS can output sine signal of up to 5GHz frequency giving an average Spurious Free Dynamic Range (SFDR) of 23.24dBc through the first Nyquist band. The DDS MMIC consumes 2.4W of DC power from a single -4.6V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 × 2.0mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A direct digital frequency synthesizer (DDFS) based on a non-equal division parabolic polynomial interpolation method is proposed in this paper. To attain high spurious free dynamic range (SDRF) and reduce area cost, a parabolic polynomial interpolation method is adopted in the proposed design to replace conventional ROM-based phase-to-sine mapper methods. Particularly, the left 1/4 of the phase range is approximated using a low-curvature parabolic curve. The proposed design is manufactured using a standard 0.18 μm CMOS technology. The maximum output frequency is 50 MHz, the core area is 1.4528 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the spurious free dynamic range (SFDR) is 68.67 dBc. The proposed DDFS outperforms prior works' SFDR and energy efficiency.

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.

A pre-realization dynamic power estimation approach for ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, which carries out the analysis of switching activity of all the major logic blocks utilized in the synthesis of ROM-less DDFS. As soon as the partitions of the π/2 and the characteristic equations for polynomial interpolation are given, the proposed approach is able to assess the overall switching activities such that the power profile of different combination of partitions and equations can be derived before any physical implementation.

By using a sine wave Digital-to-Analog Converter (DAC) to perform mapping from digital phase to sine amplitude, the ROM-less Direct Digital Frequency Synthesizer (DDFS) consumes less power than the conventional ROM lookup table approach. To further reduce the power dissipation and the die area of the sine wave DAC, two segmented sine wave DAC architectures are proposed in this paper. The optimized segmentation parameters for better performance and lower power dissipation are also discussed.

A quadrature direct digital frequency synthesizer (DDFS) was designed and implemented in a 1.2 µm CMOS process using two non-linear resistor string DACs. These DACs are used in place of the phase-to-amplitude ROM look-up tables and the linear DACs in a conventional quadrature DDFS to give a low power design. At 25 MHz clock frequency, the DDFS dissipates less than 4 mW at 3.3 V and has SFDR better than 55 dBc at low synthesized frequencies.

In this paper, a quadrature direct digital frequency synthesizer (DDFS) based on a new angle rotation algorithm is presented. It is shown that the proposed architecture features higher spectral purity,, reduced hardware cost, power consumption, and tuning. latency when compared to previously presented designs. The introduced DDFS produces 16-bit sine and cosine waveforms with a spurious free dynamic range (SFDR) of 114 dBc. The design was implemented using a 0.35 /spl mu/m CMOS technology. It occupies an area of 0.46 mm/sup 2/ and dissipates 115 mW at 3.3 V supply voltage and 100 MHz clock.

Direct digital frequency synthesis (DDS) as an indispensable key technology for modern communication systems, is widely used in digital communications, satellite communications, aerospace and high-speed instrumentation. In practical applications, DDS technology is usually required to generate different kinds of communication signals. In view of the fact that there is no related research on spurious signals when DDS technology generates communication signals, this paper based on a DDS model that can generate arbitrary symbol rate communication signals, analyzes spurious signals of the structure in detail. The conclusions of this paper can be used for the spur evaluation and parameter selection in DDS engineering applications. At the same time, this paper provides a theoretical basis for the low spurious design of DDS, and has certain reference value for DDS to generate communication signals.

In this paper, we analyze the design and the possible optimization methods of the direct digital frequency synthesizer (DDFS) based on quadratic approximation. The goal is to design a DDFS with reduced hardware cost and very high spectral purity. For the DDFS based on quadratic approximation, there is a trade-off between the size of the memory and the approximation logic. We show that by exploring this trade-off, it is possible to design a DDFS which requires less hardware and features higher spectral purity than the previously presented solutions. By using the proposed design method, a DDFS that generates 16-bit sinusoidal waves with a spurious free dynamic range of 132 dBc (126 dBc if the phase is truncated) was designed.

An improved CORDIC (Coordinated Rotation Digital Computer) algorithm based on small capacity ROM is proposed. The method of angle binary to bipolar recoding eliminates the calculation of the remaining angle and simplifies the calculation of the scaling factor, at the same time, loop iteration and merge iteration reduce the delay of the system. This work implemented a direct digital frequency synthesizer (DDFS) based on this algorithm. By means of four-channel parallel computing, the system clock is reduced to 250MHz and the sampling rate of DDFS is increased to 1GHz. The phase accumulator is optimized with length configurable module and the addition and subtraction configurable Arithmetic Logical Unit (ALU), the frequency of the system clock is increased and the resource consumption is reduced than the original one. This work takes the 24-bit output bit width as an example to analyze the output effect of DDFS. The results indicate that the maximum absolute error of the output cosine in this work is 6.794×10−7 , and it has an order of magnitude improvement compared with the scheme of the same type algorithm; the spurious-free dynamic range (SFDR) is 86.77dB when the DDFS output is maximum up to 350MHz,it is improving 22.09% than the scheme based on the 12-bit ROM. Meanwhile, the consumption of resources is reduced to 73.3% of the original one, and the delay of the output is only 36ns.

An experimental platform was developed to investigate the effects of audible sound (20 Hz to 20 MHz) on plant growth promotion, which included a microcontroller-based embedded system for audible sound adjustment and analysis. The direct digital frequency synthesis (DDFS) method was used to generate various waveforms of sound in the platform. Soundproof glass and mufflers were used to reduce background noise. The developed system was tested on various plants, including hydroponic tomatoes, celery and mung bean. The testing results showed that the developed platform could produce pure tone and mixing audible sound with high stability and accuracy, make octave analysis of the sound under experimental environments, and the background noise in the testing chamber of the platform was lower than 55 dB(A) when the compression engine was working. The developed experimental platform has a great potential on facilitating scientific research on acoustic biology effects on plants and collecting real-time experimental data. Keywords: plant growth, background noise, acoustic biology effect, direct digital frequency synthesis, sound sensor DOI: 10.3965/j.ijabe.20150805.1556 Citation: Cai W M, Zhu S M, Wang N, He H N, Ying B H. Design of an experimental platform to investigate the effects of audible sounds on plant growth. Int J Agric & Biol Eng, 2015; 8(5): 162－169.

An 800 MSPS quadrature Direct Digital Frequency Synthesizer (DDFS) with an integrated 13-bit nonlinear DAC and a 200 MHz spur-rejection filter is presented. The system consists of a 10 ns latency ROM-less DDFS and a sine-weighted, current-steering DAC with a layout technique conducive to the DDFS algorithm. A 200 MHz active OTA-RC spur-rejection filter follows the DDFS-DAC giving > 60 dB rejection at 600 MHz with an IIP3 of 25 dBm. The system achieves an SFDR ≈ 33 dB and a total instantaneous hopping time of 15 ns. The system is designed and fabricated in a 0.13 μm CMOS technology, has a total chip area of 2.54 mm × 2.96 mm, and consumes 420 mW of power.

This brief presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> integrated over a 100MHz bandwidth with 28.25Hz resolution while consuming less than 3mW at sampling clock 3.12GHz. The proposed DDFS is fabricated in a 0.9V TSMC 7nm CMOS process and occupies a core area of only 0.014mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .