A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

Adiabatic logic circuit can be considered as one of the most attractive solutions for low power circuits. This paper treats a design optimization of Two-Level Adiabatic Logic (2LAL) circuit which has a relatively simple structure and an excellent low-power performance compared with many other asymptotically adiabatic or quasi-adiabatic logic families, while it needs a large number of timing buffers for "decomputation". We focus on "early decompute" technique for fully pipelined 2LAL, and proposes an ILP approach to the optimization of early decompute for minimizing hardware cost. First we show that our hardware minimization problem can be reduced into "Stable Set" problem, and then we derive its ILP formulation. The superiority of the proposed method is evaluated using ISCAS-85 benchmark circuits.

This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.

With the increasing growth of VLSI technologies the number of gates per chip is constantly increasing, as a result power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issue in low power circuits in VLSI design. Adiabatic logic is a promising technique used in low power VLSI circuits to achieve high level of performance with limiting power consumption. In Adiabatic logic, power consumption /dissipation occurring at the time of switching event is avoidable as the power supply retrieve the charge from node capacitance without heat generation which is contradict to conventional CMOS logic style and also power saving more than 50% is achievable in case of partial adiabatic circuits when compared to conventional CMOS circuits but with increase in circuit complexity. The simulation is carried out for half adder and half subtractor using 180nm CMOS technology in Cadence Virtuoso environment. From the obtained results, it is found that average power saving is more for half adder and half subtractor implemented using PFAL technique when compared to other techniques of partial adiabatic logic including conventional CMOS logic.

A new FinFET-based adiabatic NAND logic circuit with Self-Adjustment of Rail Potential (SARP) is proposed. The proposed logic provides reduced power consumption when compared to conventional CMOS and adiabatic circuits. A new FinFET-based adiabatic logic is implemented based on Complementary Energy Path structure. The proposed design reduces the second-order effects, short-Channel effects occurring in Conventional CMOS circuits. The performance of the proposed SARP-FinFET-based adiabatic NAND gate is dominant when compared to the SARP-CMOS-based adiabatic NAND gate. The proposed adiabatic circuits are designed using double gate FinFET using predictive technology models (PTM) in 32 nm Technology using Synopsis HSPICE. The experimental results for the proposed adiabatic FinFET design demonstrate their effectiveness with energy consumption and power optimization.

In this paper we describe an approach for using the true single phase clock (TSPC) circuit style for the implementation of a scalable, pre-loadable pre-scaler. By utilization of a signed digit (SD) based redundant adder cell the execution of the necessary addition operation can be performed in only one clock cycle, independent of the length of the applied operators. The development process for this SD-adder cell by reorganization and partitioning of the necessary logic in connection with an enhancement of the TSPC circuit style will be discussed. The determination of the zero-crossing is also as far as possible independent from the word length by deployment of a TSPC OR-cell. Furthermore, a reference implementation of a 8-digit pre-scaler circuit operating at 1 GHz with a 5 V power supply in a 0.6 /spl mu/m AMS CMOS process will be presented. The goal of this paper is to develop a strategy for the implementation of pre-scaler circuits based on redundant arithmetic, which can operate at high frequencies. The comparison with the results of other implementations illustrate the advantages of our approach.

Multiple-valued logic has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. Lowenergy (adiabatic) logic circuits have also been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional DC power supply, these adiabatic logic circuits use ‘AC’ power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper we describe the adiabatic operation of a quaternary logic circuit.

PurposeA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.Design/methodology/approachThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.FindingsThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.Originality/valueThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation

The interest for ultra-low power integrated circuits in the recent past has guided the research community to establish the proposal of several adiabatic logic circuits in which the energy stored can be efficiently recycled. Many of these architectures suffer from problems like glitch & huge number of transistors as compared to conventional CMOS, which stop them to be used in practical scenario. As a consequence, we tried to come up with a new circuit that could address the above said limitations. In this work, we have proposed a new adiabatic logic where glitches are reduced drastically such that Logic 0 & Logic 1 level looks almost like what we generally have in conventional CMOS circuit output. The new logic is applied to design NOT, NAND & NOR gate as these are the fundamental building blocks of any digital system. The simulation of the circuits is done in 180 nm Technology and a significant savings in power and energy has been achieved after comparing with the conventional CMOS and a few previous well known adiabatic logics.

In the present scenario, power consumption is a vital issue in low power circuit design. The adiabatic logic and the conventional CMOS logic styles are widely used in low power VLSI design. The power saving is more effective in adiabatic circuit compared to conventional CMOS logic. In compared to gate diffusion technique, an adiabatic logic required more number of transistors, and more power is needed. The objective of this paper is to design and implement of 4:1 multiplexer using different adiabatic logic styles and gate diffusion technique and compares them in terms of the power dissipation and transistor count. The simulation has been done by using the EDA Tanner tools.KeywordsAdiabatic logicECRLPFAL2N-2N2PAdiabatic array logicPCRLGDIPower dissipationTransistor count

The design of a dual modulus prescaler 32/33 in a 0.35μm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called Extended True Single Phase Clock (E-TSPC), an extension of the True Single Phase Clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

The frequency divider, as an important component of a Phase-Locked Loop (PLL), has its input frequency for normal operation as a critical issue. This paper presents a low-noise, high-speed programmable frequency divider with automatic retiming system. The divider utilizes a novel 2/3 prescaler based on Extended True Single Phase Clock (E-TSPC) structure with logic gate merged, employs 6 stages of 2/3 frequency divider cell based on the traditional True Single Phase Clock (TSPC) structure, and incorporates a D flip-flop (DFF) as a retiming element to reduce the output noise of the divider. Furthermore, an automatic retiming system is implemented to prevent metastability during the retiming process. The divider is implemented in a 28nm CMOS process and features a programmable frequency division ratio between 128 and 255. The proposed prescaler has only a power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$475.6\mu \mathrm{W}$</tex> in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\div 3$</tex> mode with a maximum operating frequency of 25GHz. Under a 20 GHz input frequency with a division ratio of 200, the overall divider's output phase noise is -181.8 dBc/Hz at 10 MHz offset.

Abstract. Losses due to gate-leakage-currents become more dominant in new technologies as gate leakage currents increase exponentially with decreasing gate oxide thickness. The most promising Adiabatic Logic (AL) families use a clocked power supply with four states. Hence, the full VDD voltage drops over an AL gate only for a quarter of the clock cycle, causing a full gate leakage only for a quarter of the clock period. The rising and falling ramps of the clocked power supply lead to an additional energy consumption by gate leakage. This energy is smaller than the fraction caused by the constant VDD drop, because the gate leakage exponentially depends on the voltage across the oxide. To obtain smaller energy consumption, Improved Adiabatic Logic (IAL) has been introduced. IAL swaps all n- and p-channel transistors. The logic blocks are built of p-channel devices which show gate tunneling currents significantly smaller than in n-channel devices. Using IAL instead of conventional AL allows an additional reduction of the energy consumption caused by gate leakage. Simulations based on a 90nm CMOS process show a lowering in gate leakage energy consumption for AL by a factor of 1.5 compared to static CMOS. For IAL the factor is up to 4. The achievable reduction varies depending on the considered AL family and the complexity of the gate.

Computational speed of basic data path elements such as adders plays a crucial role in performance of digital and signal processing systems. Among various adder architectures, carry select adder (CSLA) has better performance in terms of speed in comparison with others. However, this merit is accompanied by its high power dissipation and area occupancy due to redundant computing elements used in each stage hence limiting its application. Power dissipation in these adders can be minimized by various low power implementation techniques such as reversible logic gates, multi-V th approach, and adiabatic logic. Among these low power approaches, adiabatic logic proves to be more efficient in comparison with other low power approaches. In the proposed work, 180 nm CMOS technology in CADENCE environment is used to carry out the design and analysis of both conventional and proposed CSLA architectures. Power dissipation in this proposed 8-bit CSLA architecture reduces by about 82% as compared to conventional 8-bit CSLA adder architecture. Further, the computational delay is also reduced when compared with the conventional 8-bit CSLA architecture. It is noteworthy that delay in adiabatic logic circuits greatly depends on frequency of operation [1].

Adiabatic logic saves energy compared to static CMOS by charging the outputs efficiently and by recovering charge from the outputs. For the most promising adiabatic logic families a four phase power-clock is used, that can be generated in an energy efficient manner by using a synchronized 2N2P LC oscillator. Different input patterns to the circuit lead to different capacitive loads seen by the oscillator. A method to investigate the impact of the pattern-induced capacitive variations on the LC oscillator is presented in this paper. The circuit should be disconnected from the power-clock in idle times, when no data is processed, as adiabatic logic consumes energy also if no change occurs in the input data. We propose an easy to implement, powerful and fast method to switch off the oscillator by holding the synchronization signals constant. This makes adiabatic systems even more energy efficient.