Performance Analysis of Multiplexer Using Adiabatic Logic and Gate Diffusion Technique

With the increasing growth of VLSI technologies the number of gates per chip is constantly increasing, as a result power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issue in low power circuits in VLSI design. Adiabatic logic is a promising technique used in low power VLSI circuits to achieve high level of performance with limiting power consumption. In Adiabatic logic, power consumption /dissipation occurring at the time of switching event is avoidable as the power supply retrieve the charge from node capacitance without heat generation which is contradict to conventional CMOS logic style and also power saving more than 50% is achievable in case of partial adiabatic circuits when compared to conventional CMOS circuits but with increase in circuit complexity. The simulation is carried out for half adder and half subtractor using 180nm CMOS technology in Cadence Virtuoso environment. From the obtained results, it is found that average power saving is more for half adder and half subtractor implemented using PFAL technique when compared to other techniques of partial adiabatic logic including conventional CMOS logic.

The appetency for high performance electronic devices in today's time imposes constraints on designers to make low power circuits. Various circuit styles and techniques are adopted to fulfill the aim. Adiabatic logic style is one of the most preferred logic styles for achieving high energy efficiency in the circuits. In this paper, the use of adiabatic logic style in the implementation of pre-scalars is demonstrated. The Diode Free Adiabatic Logic (DFAL) family has been chosen for the realization. The DFAL based divide-by-3 and divide-by-5 pre-scalars circuit maintaining 50% duty cycle are proposed. The functionality of the circuits is verified through TSPICE simulations by using 180nm CMOS technology parameters. Their performance is compared with the CMOS counterparts corroborating with the superiority of DFAL pre-scalars over CMOS logic in terms of power dissipation and power delay product.

In this paper, a comparative study of transistor based various adiabatic logic styles has been done thoroughly for the first time in the near-threshold regime. A uniform simulation environment is taken into consideration for exact results. To verify the workability of the adiabatic logic styles in the near threshold regime, extensive simulations have been done considering 22nm technology. The study is based on the effect of the supply voltage, temperature, and capacitive load on power dissipations in various logic styles. Notable changes in consumption of power and degradation of output waveforms at different stages have been observed among the diverse set of logic styles chosen for analysis. From the simulation results Efficient Charge Recovery Logic (ECRL) is found to be most efficient in near-threshold regime and perform without sacrificing noise immunity and driving ability and consuming least power.

A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.

We present a sinusoidal single phase power clock generation method for low energy (adiabatic) circuits. In this paper radio frequency resonant DC-AC converter is proposed as power clock generator. We have also obtained square wave from RC oscillator consisting of cascaded NOT gates. This square wave and its inverted and delayed version are used as gate-drive signals for MOSFET switches those are used in the LC resonant circuit. A 2∶1 MUX, implemented in Pass-transistor Adiabatic Logic (PAL) style, is operated from this power clock to illustrate power saving. It is observed that power dissipation of PAL 2∶1 MUX is about 26 times lesser than that of conventional CMOS 2∶1 MUX. If for 2∶1 MUX, PAL logic is implemented in place of conventional CMOS logic, power saving per MUX that is achieved is about 96%. Also power dissipated in Power Clock is found to be equivalent to power dissipated in five CMOS 2∶1 MUXs. 0.35µm technology is used for obtaining simulation results.

This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic.

In digital circuits, shift registers are used as the basic memory units. This paper presents a low power adiabatic Universal Shift Register, which can perform both serial and parallel shift operations. Since power dissipation is a critical factor many low power dissipation techniques have been proposed but most of these techniques have some trade-offs. Adiabatic logic technique as compared to that of a conventional CMOS technique shows promising results. A type of adiabatic technique, DFAL (Diode Free Adiabatic Logic), has been studied in this paper and NOR gate, NAND gate, XOR gate, D Flip-Flop and Universal Shift Register have been designed using this configuration. DFAL circuits are analyzed based on transistor count, power dissipation and delay. All the circuits are simulated in Pyxis (Mentor Graphics) 180nm technology at 1.8V.

Wireless communication exhibits the highest energy consumption in wireless sensor networks nodes. Due to their limited energy supply from batteries, the low power VLSI designs have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only can enhance battery life but also can avoid the overheating problem. By employing a more appropriate processing element, the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Multi-Bit Flip-Flop Merging (MBFM) technique for on-the-node data processing in wireless sensor networks using Parallel Prefix Operations (PPO) and data locality in hardware. Besides power reduction the objective of minimizing area and delay is also considered.

In recent years, VLSI designers are more concerned about power minimization of digital circuits and in this field the reversible logic design has emerged as one of the powerful tool due to its low power consumption feature. Adiabatic logic is also an attractive solution for energy minimization. In this paper, we have combined both the adiabatic and reversible logic. The basic reversible logic gates FEYNMAN and TOFFOLI gates based on ECRL, 2PASCL and CMOS logics are evaluated on CADENCE VIRTUOSO EDA tool using UMC 180 nm technology. Simulation results show that 2PASCL adiabatic logic is better in terms of power dissipation than ECRL and CMOS in the range of 10MHz–100MHz.

A novel, energy efficient and power analysis robust logic style called the charge balancing symmetric pre-resolve adiabatic logic (CBSPAL) is proposed to overcome the susceptibility of cryptosystems against side channel power analysis attacks. It employs differential cascode logic tree structure with a pre-resolving feature, which realises improved energy efficiency by minimising non-adiabatic loss and leakage current. The energy efficiency of the proposed logic against static complementary metal oxide semiconductor (CMOS) and other existing secure adiabatic logic styles is proved. Energy deviation for the different input transitions of the individual logic gates, namely, buffer/NOT, AND/NAND and XOR/XNOR is found to be very minimal and it validates the immunity of the proposed logic against power analysis attacks. SPICE simulation of 4-bit add-round structure implementation using CBSPAL shows an energy saving of 89.5% compared to static CMOS implementation at a frequency of 125 MHz. Security of the proposed logic against the side channel power analysis attack is demonstrated by performing the correlation power analysis attacks as applicable for the SPICE simulations. Exhaustive SPICE simulations have been performed using the 32 nm CMOS predictive technology model libraries.

The principal objective of this work is to provide new low power solutions for VLSI design engineers. This work focuses on the reduction of power dissipation by taking advantage of adiabatic logic. The switching power requirement of conventional CMOS circuits has become a major concern in VLSI systems. In this paper new ultra low power logic called adiabatic logic or energy recovery logic is presented. We have design various DFF cells using various energy recovery logic. Power consumption is calculated by VLSI EDA Tools and compared with conventional CMOS DFF.

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The schematic edit and T-Spice of Tanner tools formed the simulation environment.

Spin Torque Transfer RAM (STT-RAM), a assuring possible choice of Static RAM for diminishing leakage power utilization. STT-RAM has the resistance of the MTJ (Magnetic Tunnel Junction) that changes based on stored data. By using differential sensing with reconfigurable cache cell, the STT-RAM performance can be improved. This scheme largely reduces the read disturbance error and average power dissipation with small reading current. Furthermore reducing the power dissipation of STT-RAM, we introduce one new approach as Adiabatic (Energy recovery) Technique. Adiabatic Technique main motive is to reduce the average power dissipation with no performance degradation. The Adiabatic logic and memory are attractive solution for low power application.