Implementation and analysis of power clock generation method for adiabetic circuits

In this paper, a comparative study of transistor based various adiabatic logic styles has been done thoroughly for the first time in the near-threshold regime. A uniform simulation environment is taken into consideration for exact results. To verify the workability of the adiabatic logic styles in the near threshold regime, extensive simulations have been done considering 22nm technology. The study is based on the effect of the supply voltage, temperature, and capacitive load on power dissipations in various logic styles. Notable changes in consumption of power and degradation of output waveforms at different stages have been observed among the diverse set of logic styles chosen for analysis. From the simulation results Efficient Charge Recovery Logic (ECRL) is found to be most efficient in near-threshold regime and perform without sacrificing noise immunity and driving ability and consuming least power.

In this paper, the first comprehensive methodology is presented for design of low power adiabatic circuits inclusive of the adiabatic core design and the power-clock generation. Prior works have focused on either designing adiabatic cores or the power clock generation circuit, only. These non-comprehensive views can misrepresent the performance savings and fail to address the opportunities at integration. In this work, a comprehensive solution is presented that also features a unique innovation for the power clock generation circuit in step-charged circuits designed with rotary traveling wave oscillators (RTWO) and adiabatic frequency dividers. In experimentation, SPICE based simulations are performed at 416 MHz and 330 MHz in the 90 nm technology node and compared to CMOS based implementations, as well as other known power-clock generation techniques. A 32-bit CMOS adder consumes 3.5× more power when compared to the proposed 32-bit ECRL adder operating at a frequency of 416 MHz. Furthermore, 1000 32-bit CMOS adders in parallel consumes 3.4× more power when compared to 1000 32-bit ECRL adders in parallel designed with the proposed architecture at a frequency of 416 MHz.

Power clock generators (PCGs) are the prevalent overhead for the adiabatic systems and mutilate all the low-power advantage from the adiabatic logic part by consuming a large portion of the total power in the clock generation circuitry (Arsalan and Shams, 2005). In addition to the PCG issues, routing multiple clock phases for adiabatic circuits is not very convenient and raises a number of cost, performance and viability issues. To get rid of the problems related to clock generation and synchronous clock routing, a new solution namely asynchronous adiabatic logic (AAL) is proposed to combing the benefits of the adiabatic logic circuits with that of asynchronous logic systems. Going asynchronous not only eliminates the need of PCGs, hence all the problems associated with the generation and routing of the clocks, it also bring all the advantages intrinsically associated with an asynchronous design such as low power and reliable logical operation.

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

In the present scenario, power consumption is a vital issue in low power circuit design. The adiabatic logic and the conventional CMOS logic styles are widely used in low power VLSI design. The power saving is more effective in adiabatic circuit compared to conventional CMOS logic. In compared to gate diffusion technique, an adiabatic logic required more number of transistors, and more power is needed. The objective of this paper is to design and implement of 4:1 multiplexer using different adiabatic logic styles and gate diffusion technique and compares them in terms of the power dissipation and transistor count. The simulation has been done by using the EDA Tanner tools.KeywordsAdiabatic logicECRLPFAL2N-2N2PAdiabatic array logicPCRLGDIPower dissipationTransistor count

The appetency for high performance electronic devices in today's time imposes constraints on designers to make low power circuits. Various circuit styles and techniques are adopted to fulfill the aim. Adiabatic logic style is one of the most preferred logic styles for achieving high energy efficiency in the circuits. In this paper, the use of adiabatic logic style in the implementation of pre-scalars is demonstrated. The Diode Free Adiabatic Logic (DFAL) family has been chosen for the realization. The DFAL based divide-by-3 and divide-by-5 pre-scalars circuit maintaining 50% duty cycle are proposed. The functionality of the circuits is verified through TSPICE simulations by using 180nm CMOS technology parameters. Their performance is compared with the CMOS counterparts corroborating with the superiority of DFAL pre-scalars over CMOS logic in terms of power dissipation and power delay product.

Due to the low-power requirement by devices deployed in Near Field Communication (NFC) application operating at low frequencies, adiabatic logic is a good candidate for their implementation and can be used to reduce energy consumption. Adiabatic logic works using an AC power-clock supply. However, generating the AC power-clock increases the energy consumption of the complete adiabatic system. A lot of work has been done on generating the AC power-clocks using resonant circuits and a handful by using the stepwise capacitor-based circuit. But the literature lacks the study of the impact of adiabatic logic families’ on the power-clock generator energy dissipation and efficiency. In this paper, we investigate the effect of adiabatic logic families working with 4-phase power-clock generators designed using a 2-StepWise Charging (SWC) circuit. The analysis of the energy dissipation for single power-clock is done taking into account the parasitic resistance and capacitance of the adiabatic logic and power-clock network. Experiments based on simulation results show that the adiabatic logic families’ impacts both the energy consumption and efficiency of the complete adiabatic system.

With the increasing growth of VLSI technologies the number of gates per chip is constantly increasing, as a result power dissipation increases and heat removal becomes complex and expensive. Therefore, power dissipation is one of the critical issue in low power circuits in VLSI design. Adiabatic logic is a promising technique used in low power VLSI circuits to achieve high level of performance with limiting power consumption. In Adiabatic logic, power consumption /dissipation occurring at the time of switching event is avoidable as the power supply retrieve the charge from node capacitance without heat generation which is contradict to conventional CMOS logic style and also power saving more than 50% is achievable in case of partial adiabatic circuits when compared to conventional CMOS circuits but with increase in circuit complexity. The simulation is carried out for half adder and half subtractor using 180nm CMOS technology in Cadence Virtuoso environment. From the obtained results, it is found that average power saving is more for half adder and half subtractor implemented using PFAL technique when compared to other techniques of partial adiabatic logic including conventional CMOS logic.

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The schematic edit and T-Spice of Tanner tools formed the simulation environment.

The energy consumption issue is efficiently addressed by adiabatic switching technique in design of low power digital circuits. Adiabatic switching technique offers the reducing in energy dissipation during switching events and recycling the load capacitance energy instead of dissipated as heat. But adiabatic circuits highly depend upon power clock and parameter variations. With the help of clocking rule, the digital circuits such as inverter and inverter chain are designed for adiabatic techniques, 2N-2N2P, Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL) and Clocked Adiabatic Logic (CAL) using TSPICE simulation. The results show high energy savings as compared to CMOS circuits in specified frequency range.

with the advancement of technology, the need for low power devices has increased. Adiabatic logic style aims at reducing the power dissipation by reusing the energy that gets dissipated in conventional CMOS circuits. The aim of this paper is to compare NOT/Buffer implemented using ECRL and TSEL (types of adiabatic logic styles) on the basis of power dissipation, delay and figure of merit for varying temperatures and frequencies under a uniform test environment. The results which are simulated using tanner version 13.0 yield that at 10 MHz TSEL performs approximately 60% more efficiently than ECRL for most of the temperatures and around 100 times better than ECRL at room temperature. For 100 MHz frequency, TSEL is superior to ECRL for all the temperatures. However, for 500 MHz, ECRL supersede TSEL by performing 62% more efficiently. At 1000 MHz, ECRL performs exceptionally better than TSEL especially at extreme temperatures. The test bench has been fabricated on a 90 nm CMOS technology.

Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.

Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

Reversible computing is considered to be a key technology to achieve an extremely high energy efficiency in future computers. In this study, we investigated the relationship between reversibility and energy dissipation in adiabatic superconductor logic. We analyzed the evolution of phase differences of Josephson junctions in the reversible quantum-flux-parametron (RQFP) gate and confirmed that the phase differences can change time reversibly, which indicates that the RQFP gate is physically, as well as logically, reversible. We calculated energy dissipation required for the RQFP gate to perform a logic operation and numerically demonstrated that the energy dissipation can fall below the thermal limit, or the Landauer bound, by lowering operation frequencies. We also investigated the 1-bit-erasure gate as a logically irreversible gate and the quasi-RQFP gate as a physically irreversible gate. We calculated the energy dissipation of these irreversible gates and showed that the energy dissipation of these gate is dominated by non-adiabatic state changes, which are induced by unwanted interactions between gates due to logical or physical irreversibility. Our results show that, in reversible computing using adiabatic superconductor logic, logical and physical reversibility are required to achieve energy dissipation smaller than the Landauer bound without non-adiabatic processes caused by gate interactions.