A novel low power flip-flop design using footless scheme

Because of the isolation of transistors, fully depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this article, the SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate (GG) circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a GG FF, a dual-feedback-recovery (DFR) FF, and a GG-dual-interconnected storage cell (DICE) FF. Irradiation results showed significant reductions in SEU cross sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100\times $ </tex-math></inline-formula> improvement over a conventional FF design, while DFR and GG-DICE designs showed no upsets for all test conditions. Further analysis was carried out to explain the SEU performance differences between the GG and DFR FF designs, and it is noted that proper layout arrangement is critical for achieving ideal SEU mitigation in this FDSOI technology node.

With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Soft-error rates (SER) of Flip-Flop (FF) designs in a 16-nm bulk FinFET technology are characterized with thermal neutron, high-energy neutron and alpha particle irradiations. Results show that the contribution of thermal-neutron-induced SER can be higher or lower than alpha-particle-induced SER for different FF designs and can be comparable to high-energy-neutron-induced SER for some FF designs. The contribution of thermal-neutron-induced SER to overall SER can be significantly higher than previously reported.

In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

The flip-flops are considered as major contributors to the power dissipation of the clocking system, which is made up of the clock provision network and storage elements (latches, flip-flops). The power- and delay-efficient new implicit-pulsed dual-edge triggering flip-flop circuit (IP-DETFF) is proposed with two latching stages by employing an implicit-pulse triggering, dual-edge clocking and reducing the number of clocked loads. This leads to the reduction of power consumption due to clock allocation tree (pclk-tree) and reduces the delay time. The dual-edge clocking technique is incorporated into this proposed design without an increment of the number of transistors and minimizes the operating frequency as half. This methodology is also employed in this proposed design to construct new latching part of the flip-flop circuit. The performance of proposed flip-flop is analyzed by simulating the circuit at 0.12[Formula: see text][Formula: see text]m CMOS (complementary metal oxide semiconductor) process technology. The simulation results show that the proposed design achieves power saving from 11.22% to 54.81%, improvement of speed from 67% to 71.50%, power-delay product (PDP) from 74.85% to 81.26 %, energy-delay product (EDP) from 87.86% to 92.4% and power-energy product (PEP) from 75.24% to 93.57% compared to the conventional flip-flops.

Single Electron Transistor (SET) is a nanoelectronic device that operates under the controlled mode of tunneled individual electrons. In this paper, a comparative analysis was performed employing SET based D-Flip flop with conventional logic D-flip flop. SET is eminent nanoscale devices that have low power dissipation, high speed and performance. The flip flop design was simulated using SIMON simulator and the stability of its operation was analyzed applying the Monte-Carlo method that represented stability with low power dissipation and matched the functionality of traditional CMOS devices.

A new design of a non-volatile magnetic flip-flop is presented. The use of a magnetic tunnel junction (MTJ) to store the information brings non-volatility to logic circuits and promises zero standby power. It is based on the thermally assisted switching (TAS) approach and the pre-charge sense amplifier. By using STMicroelectronics' CMOS 0.13um design kit and a precise TAS-MTJ compact model, transient functional simulations and Monte Carlo statistical analysis have been carried out to show, respectively, its low power and high reliability performances.

In this work, a novel power efficient pulse triggered flip flop design with minimum no. of transistors is proposed. Proposed Flip-Flop (FF) has two new feature points. First point, the pulse generation control logic is designed with single modified inverter and a pass transistor which reduces the complexity and extra switching in pulse generator circuit. Second point, signal feed through technique with some modification is devised to speed up the charging and discharging along the critical path only when needed. As a result, no. of transistors in pulse generation circuit has been reduced for power and area saving. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed FF design has the highest power-delay product performance in all FF designs under comparison.

With the advancement in the VLSI technology, the demand for low power consumption and high performance increased gradually. When the applications of data retention are considered, then the need for advanced memory units is taken into account. This requirement of enhanced memory units is incorporated with the concept of conservation of energy which is achieved by using low-power techniques. In digital circuits, flip-flops are the essential memory and timing elements. New methods and techniques needed to be developed for implementing energy-efficient low-power flip flops. This paper proposes dual edge-triggered flip-flop (DETFF) along with gating technique, one of the most reliable low-power techniques which provide one-time solution to low-power applications. The DETFF circuit based on gating technique is simulated using MENTOR GRAPHICS tool in 180 nm technology. This design is efficient in reducing power dissipation leading to the reduction in area and delay and subsequently leads to the high speed of the device.

The CMOS technology has reached its physical fundamental limit. Due to the shortcomings in CMOS like the short channel effect, doping fluctuations, leakage current, an extensive research is going on. Though various technologies have been proposed, Quantum-dot cellular automata seems to be more attractive technology. QCA is transistor less. It can replace complementary metal–oxide–semiconductor (CMOS) at nano-scale level. The novel digital technology has the advantages of reduced area, high performance. Quantum dot cellular automata requires the basic components like inverters and majority gates. In this paper three new D-Flip Flop have been proposed. The proposed D flip flops are implemented with three-input majority gate. The D Flip-Flop design shows much improvement in terms of cell count, occupation area and input to output delay. The occupation area of proposed D Flip Flop designs have been reduced to 0.05%, 0.07% and 0.78% as compared to the design given in literature. QCA designer 2.0.3 is used to design, simulate and verify the output the circuits.

In this paper, a sense amplifier based radiation hardening (RADHARD) flip flop design is presented. The sense amplifier based master stage reduces the loading to the clock network. The proposed improvement on the slave stage shortens the data to Q delay. The simulation results indicate that the proposed design has a shorter data to Q delay than the flip flop design used in Alpha 21264 microprocessors. The proposed design can be fabricated in the mainstream commercial digital complementary metal oxide semiconductor process.

Arithmetic and Logic Unit (ALU) is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor.We present guidelines for low- and ultra low-power & high performance 32- bit ALU [1] units and analyze structures for logical operations to determine the most suitable for these regions of operations for low power applications.An ALU design is then modeled in VHDL for further testing with pre-manufactured parts of the 32 bit ALU using XILINX ISE tools. A novel method that chooses better designs of flipflops and latches in different places of the data path, based on the data and clock activities.Our simulation results indicate that, for the 180nm-65nm CMOS technologies [6] it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

The object overlaying operation is one of the most important operations in the Geographical Information Systems and spatial data application. The object overlaying is costly operation due to the amount of data processed during the performing of this operation. One technique to speed up an intensive computational operation is to implement a hardware circuit. This paper presents a low power and high performance core that can be embedded in graphical processors and applications specific chips. It demonstrates the effectiveness of prototyping a core and shows how different design decisions (such cache memory size, memory address generation...) are taken. The core has been prototyped using 0.6 /spl mu/m CMOS (three metal) technology, the prototype core is modular. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype shows that it is has a maximum delay of 3.2/spl times/10/sup -9/ s, and the power consumption is 0.376 mW. The simulation results indicate a considerably gain in the speed up of the operation and low power consumption.

Analysis of IPWR neutronic-thermohydraulic operation characteristics under low power condition