Analysis of flip flop design using nanoelectronic single electron transistor

With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

The CMOS technology has reached its physical fundamental limit. Due to the shortcomings in CMOS like the short channel effect, doping fluctuations, leakage current, an extensive research is going on. Though various technologies have been proposed, Quantum-dot cellular automata seems to be more attractive technology. QCA is transistor less. It can replace complementary metal–oxide–semiconductor (CMOS) at nano-scale level. The novel digital technology has the advantages of reduced area, high performance. Quantum dot cellular automata requires the basic components like inverters and majority gates. In this paper three new D-Flip Flop have been proposed. The proposed D flip flops are implemented with three-input majority gate. The D Flip-Flop design shows much improvement in terms of cell count, occupation area and input to output delay. The occupation area of proposed D Flip Flop designs have been reduced to 0.05%, 0.07% and 0.78% as compared to the design given in literature. QCA designer 2.0.3 is used to design, simulate and verify the output the circuits.

Since the last decade Single electronics fascinated researchers worldwide owing to its Nano feature size, ultra-low power dissipation and high speed like novel device functionalities. But the fragility is that it suffers from few intrinsic limitations. Besides, it has been revealed that CMOS and Single Electronics are rather complementary and hybridizing them diminishes the shortcomings of each other. To the contrary hybrid CMOS-Single Electron Transistors combine both the merits of Single Electron Transistors and CMOS devices and thus it ensures to be a more convenient realization for nanometer-scale circuit design. But CMOS and Single Electron Transistors are unique in nature and require two different simulating environments; thus they have to be simulated separately. Hence two distinctive simulators are used to simulate hybrid CMOS Single Electron Transistor and it is typically more time consuming. In this regard the authors here demonstrate a probable approach to simulate both CMOS and SET in one simulator. For exemplifying the authors report a hybrid CMOS-Single Electron Transistor PLA ADDER gate using MATLAB simulator. The results mimic the ADDER logic adequately.

The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.

An implementation method of cellular neural networks (CNN) based on a novel complimentary metal-oxide-semiconductor (CMOS) and single electron transistor (SET) hybrid structure named SETMOS, is proposed in this paper. The main building blocks including cell core circuit, feedback template and control template circuits are designed by the characteristic of negative differential resistance (NDR) of SETMOS and current mirror. Finally, a CNN is constructed and applied in image processing on connected component detector (CCD) and shadow detector (SD). The computer simulation results show that the designed SETMOS CNN circuits, compared to traditional CNN hardware circuits, are suitable for various scale CNN implementation because of simpler structure, lower power dissipation, faster response and higher integrated density. To a certain degree, this kind of designed structure makes it practicability and reliability in image processing.

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a 27μm thick flexible polyimide substrate using a NMOS only, single gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor technology (TFT). Reliable response of the D-FF was noticed from measurements up to a clock and an input signal frequency of 20 MHz and 2 MHz, respectively. Further, with an output voltage swing of 60%, D-FF functionality was observed up to clock and input signal frequencies of 25 MHz and 3 MHz, respectively. This circuit has shown a power dissipation of 140 μW including buffers and the figure of merit (FOM) of 142 MHz/mW, which is almost a 52% improvement compared to the state-of-the-art. In addition, this D-FF is employed in the implementation of an 11-bit up/down (U/D) counter. The U/D counter has shown a reliable operation up to an operating frequency of 8MHz with a power consumption of 4.8 mW. Both circuits were characterized at a low supply voltage of 3V, occupying an active area of 0.144 mm and 4.32 mm, respectively. These circuits would find potential application in biomedical wearable devices.

A low power true-single-phase clocking flip-flop (FF) design by using FootLess scheme named FLFF design targeting low VDD and low power operations is proposed. It is adapted from a recently presented FF design and achieves circuit simplification by using hybrid logic style. The optimization measure leads to a new design featuring better both power and speed performances. Based on the simulation results, the proposed design outperforms the conventional transmission gate flip-flop (TGFF) by 84% in energy. An 8-bit Johnson-counter consisting of the proposed FF design is developed and implemented. For the target 250 MHz working frequency, the proposed design achieves over 48.3% power saving with 14.6% area reducing.

In this paper, a new version of non-ideal model 08-bit current mode pipeline ADC has been developed. It is based on Matlab and Simulink environment with special focus given to the analog building blocks. Those blocks are current Sample-and-Hold(S/H), current SubADC and current Sub-DAC. In this model, the sub-ADC is implemented by two current comparators and encoder logic circuit. For the current S/H and sub-DAC, they are implemented by using a switch current and current source. The main advantage of current mode approach is its low power dissipation, low cost and high speed. However, there are some technical limitations; using the model and running the simulation with the introduction of the main non idealities components such as a current offset, clock feed through, charge injection, clock jitter, switching noise, mismatch errors and non idealities in current amplifier, demonstrated clear degradation of the performance of the ADC.

In this paper, handwritten farsi numeral recognition task (0-9) is developed using Hamming neural network circuit based on single electron transistors. simulations were done using Hspice and MATLAB softwares, which in comparison with SIMON software to have high speed in simulink area.

Latch and flip-flop design in QCA technology with minimum number of cells

The present paper discusses charge stability and conductance analyses of benzene- and zigzag graphene fragment-based single-electron transistors (SETs) operating in the Coulomb blockade regime. Graphene and benzene are modeled using density functional theory-based ab initio analyses, treating the interaction between graphene/benzene and the SET environment self-consistently. The devices consist of an oriented graphene/benzene island coupled with source and drain electrodes. The charging energy as a function of the external gate potential has been analyzed to verify the dependence of the charge stability and conductance of the oriented SETs on the source/drain bias and gate potential. Comparative analysis of these models shows that the SET with vertically oriented graphene is more stable and has better conductance in comparison with the benzene-based SET.

This chapter focuses on the approach of nanotechnology toward nanoelectronics, various nanoelectronic devices, and their emerging applications in the various fields of life. It confines the people discussion to solid-state quantum effect and single electron devices. Solid-state quantum effect devices can be divided as follows: quantum dots, resonant tunneling diodes, and single electron transistors. Quantum dots of large dimensions from semiconductor material are synthesized by the top-down approach. A quantum dot solar cell utilizes quantum dots as the absorbing photovoltaic material. This chapter explains the functions and applications of various solid-state devices, along with the evolution of nanoelectronic devices from the microelectronic devices and circuits. This worldwide enterprise of engineering nanoscale devices is still ongoing, and it will definitely transform our computing and technology infrastructure in the future.

Low power high speed and high precision comparator circuits are studied. Dynamic comparators are key building block for the implementation of analog to digital converters, sense amplifiers. High precision, low voltage operation, lower power consumption, high speed, less offset voltage and more reliability and are some of the important factors in designing the dynamic comparators. Since one circuit cannot provide all the mentioned properties, attempt is being made to study the performance of some dynamic comparators and compare their properties to ease the selection of suitable comparator circuit depending on the application. The circuits were rebuilt using GPDK (General Purpose Design Kit) 180nm CMOS technology in Cadence virtuoso tool.