A novel programmable wide swing buffer for OLED source driver

To meet the requirement of the battery charging characteristics and electric vehicle interoperability, wide power range and wide voltage range are important for the wireless electric vehicle (EV) charging system. Hence, ensuring zero voltage switching (ZVS) and high efficiency over the wide operating range is a hot issue but not well resolved. To address the current state of research, an efficiency-oriented control strategy is proposed for LCC-S compensated Wireless Power Transfer (WPT) system to achieve minimum ZVS current over a wide voltage and power regulation range. Based on the accurate harmonic-considered time-domain model, a universal design method for system parameters under the worst ZVS current conditions within wide operation range is proposed. Then, the universal explicit expression at the unit voltage gain point is given. Moreover, based on the simplified fitting method of piecewise bi-quadratic interpolation (PBQI), minimum ZVS current and minimum non-active current can be ensured over the full output voltage and output power range. A 3.3 kW prototype has been built to verify that the converter can realize ZVS within the whole voltage range, the measured peak efficiency is about 95.2%.

본 논문에서는 특별한 보정기법 없이 채널 간 오프셋 부정합 문제를 최소화한 2채널 time-interleaved (T-I ) 구조의 10비트 120MS/s 파이프라인 SAR ADC를 제안한다. 제안하는 ADC는 4비트-7비트 기반의 2단 파이프라인 구조 및 2채널 T-I 구조를 동시에 적용하여 전력소모를 최소화하면서 빠른 변환속도를 구현하였다. 채널 간에 비교기 및 잔류전압 증폭기 등 아날로그 회로를 공유함으로써 일반적인 T-I 구조에서 선형성을 제한하는 채널 간 오프셋 부정합 문제를 추가적인 보정기법 없이 최소화할 뿐만 아니라 전력소모 및 면적을 감소시켰다. 고속 동작을 위해 SAR 로직에는 범용 D 플립플롭 대신 TSPC D 플립플롭을 사용하여 SAR 로직에서의 지연시간을 최소화하면서 사용되는 트랜지스터의 수도 절반 수준으로 줄임으로써 전력소모 및 면적을 최소화하였다. 한편 제안하는 ADC는 기준전압 구동회로를 3가지로 분리하여, 4비트 및 7비트 기반의 SAR 동작, 잔류전압 증폭 등 서로 다른 스위칭 동작으로 인해 발생하는 기준전압 간섭 및 채널 간 이득 부정합 문제를 최소화하였다. 시제품 ADC는 고속 SAR 동작을 위한 높은 주파수의 클록을 온-칩 클록 생성회로를 통해 생성하였으며, 외부에서 duty cycle을 조절할 수 있도록 설계하였다. 시제품 ADC는 45nm CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 10비트 해상도에서 각각 최대 0.69LSB, 0.77LSB이며, 120MS/s 동작속도에서 동적 성능은 최대 50.9dB의 SNDR 및 59.7dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 0.36mm2이며, 1.1V 전원전압에서 8.8mW의 전력을 소모한다.

The isolated high-voltage gain DAB converter has extensive and significant applications in data centers, electric vehicles, and space power systems. Owing to the hardship for traditional DAB converters to attain high conversion efficiency over a wide output voltage range, this article presents a novel type of isolated hybrid three-level dc converter. Incorporating the boost converter into the traditional hybrid T-type three-level converter expands the output voltage range of the converter. Based on this, addressing the issue of increased conduction loss and decreased conversion efficiency caused by the excessive RMS value of the inductor current in the converter, a control strategy based on minimizing the RMS value of the inductor current is proposed. Simultaneously, in order to reduce the switching loss, the conditions for achieving ZVS/ZCS soft switching in the converter are analyzed. Finally, a 100 V/15–55 V converter experimental prototype is designed and established, and the performance of the new dc converter is experimentally examined. The experimental results demonstrate that the proposed new dc converter can not only achieve a high voltage gain but also attain high conversion efficiency within a wide output voltage range.

Traditional dual-band receivers are required two independent groups of receivers to receive the signals of different frequency. However, the two groups of receivers will result in the issues of large chip area and power consumption in RF system design and do not meet the costs. In this thesis, a dual-band (10/24 GHz) monopulse receiver will be discussed and implemented to apply in wireless sensors of intruder detection. These circuits of the receiver will be designed by using CMOS process, and integrate all circuits with GIPD process. The design of passive components and active circuits fabricated in GIPD and CMOS process will be discussed separately in the chapter 2 and 3, respectively. In the passive part, a dual-band of 180o coupler and a SPDT broadband switch are implemented in GIPD and CMOS process, respectively. In the active part, the circuits consist of two dual-band LNAs and two broadband down-conversion mixers which are all realized in CMOS process. Finally, the theory and design of the proposed integrated dual-band monopulse receiver will be detailed. Compared to the traditional monopulse receivers, the greatest advantage of this architecture is the lower noise figure of overall receiver and smaller the coupling effect between the signals. The proposed architecture of receiving system also can detect the trajectory of object (azimuth and distance). Finally, CMOS chip will be directly integrated in flip-chip form. It can avoid the problems of complex signal traces, size reduction and the coupling or interference between the signals when use the traditional wire-bonding technology. By introducing this design method, the goal of system-on-chip can be achieved.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-pm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm 2 and 1.6 W, respectively.

This paper proposes a photovoltaic (PV) string-level isolated DC–DC power optimizer with wide voltage range. A hybrid control scheme in which pulse frequency modulation (PFM) control and pulse width modulation (PWM) control are combined with a variable switching frequency is employed to regulate the wide PV voltage range. By adjusting the switching frequency in the above region during the PWM control process, the circulating current period can be eliminated and the turn-on period of the bidirectional switch of the dual-bridge LLC (DBLLC) resonant converter is reduced compared to that with a conventional PWM control scheme with a fixed switching frequency, resulting in better switching and conduction loss. Soft start-up control under a no-load condition is proposed to charge the DC-link electrolytic capacitor from 0 V. A laboratory prototype of a 6.25 kW DBLLC resonant converter with a transformer, including integrated resonant inductance, is built and tested in order to verify the performance and theoretical claims.

The drive to reduce the charging time and energy loss in electric vehicles (EVs) has led to increasing battery voltages to 800 V, 1000 V, 1.25 kV, and 1.5 kV, posing new challenges for designing EV fast chargers, especially for heavy-duty EVs. Two-stage converters, comprising isolated and regulated dc-dc stages, are emerging for their superior performance. This article proposes a novel two-stage bidirectional dc-dc converter with an extremely wide operating voltage range. The design features a dual-transformer reconfigurable three-leg converter (DTR3LC) in the first stage, an interleaved reconfigurable buck converter (IRBC) in the second stage, and four auxiliary switches for reconfiguration. These switches enable the secondary side of the DTR3LC to switch between parallel and series connections, which are then regulated by the IRBC, resulting in high efficiency and low current ripple across a wide voltage range. A 1-kW scaled-down laboratory experimental setup was developed and tested with an input voltage of 80 V to charge EV batteries ranging from 15 to 150 V, achieving a maximum efficiency of 95.32% at 150 V.

In household applications, the power router is a cost‐effective device for AC/DC power conversion. To make it compatible with various types of DC loads without introducing extra power conversion stages, it is important that the power router can work in an extremely wide DC voltage range. However, this poses great challenges for the controller design. To address this concern, a double mode control scheme is proposed. The high frequency resonant DC/DC converter is employed together with a DC/AC converter to form the power router. Its circuit features on voltage gain and active power ratio are presented to guide the accurate controller design. Mode I is designed to ensure the high efficiency DC/DC conversion while the desired output DC voltage of power router is tracked by a DC/AC converter. For mode II, the phase shift scheme is triggered to eliminate the loss induced by the reactive power, and the desired output DC voltage is adjusted by DC/DC converter. Mode I and II cooperate to guarantee the wide DC voltage range to satisfy different load requirements. The experimental validation in a lab‐scale power router prototype shows that the proposed scheme not only provides extremely wide voltage range, but also guarantees high efficiency by effectively tracking the resonant frequency.

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in <TEX>${\pm}5%$</TEX> and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 <TEX>${\mu}m$</TEX> X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

A soft-switching extended secondary universal current-fed converter (ESUC) has been proposed, analyzed, and designed. The proposed converter accommodates a wide source voltage range to cover several sources to interface through extended secondary-circuit and hybrid modulation. Proposed fixed frequency hybrid modulation and design achieves soft-switching of semiconductor devices under all operating conditions. It is therefore suitable to be universally adopted for solar photovoltaic (PV), fuel cell, and battery applications. Current-fed technology is suitable for such sources (low voltage, high current). Experimental results are illustrated to verify the claims and to show the performance of the converter over a wide input voltage range of 20-60 V with load variation.

This paper presents a 2.4 GHz RF front end for use in a wireless powered micro neural interface systems. The front end consists of a matching network and a two stage rectifier. A programmable current source is included for circuit validation. There is a great and growing need for wirelessly powering biological implants. Specifically, we are addressing a need for neural sensors and stimulators were total power dissipation must be less than 1 mW for safety reasons. Subthreshold CMOS analog circuits operate successfully over a large range of supply voltages. A wide range of output voltages from -250 mV up to 2.4V are observed when varying the load current at a fixed input power and vice versa. The total chip area including bond pads is 0.730 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .The designs were fabricated using peregrine 0.5 micron silicon on sapphire process.

A chip-area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated ΔV GS of NMOS transistors is proposed in this paper. The ΔV GS of two different-V th NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary -to-absolute-temperature (CTAT) and proportional-to-absolute- temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC ΔV GS to a diode-connected NMOS and provide the low-TC V REF . Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-μm CMOS process. An average TC of 27.26 ppm/°C is measured across 6 dies with a standard derivation of 16.40 ppm/°C over −40 to 80 °C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than −62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm2.

A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure is used without digital calibration which largely saves the power consumption, chip area and cost. And a differential resistive reference ladder is designed to minimize the inaccuracy of the reference voltage. The proposed ADC dissipates 34 mW power from a 1.8 V supply while operating at 4 GHz. This chip has been fabricated in 0.18 μm 1P6M CMOS process and the ADC achieves 1.86-bit effective number of bits (ENOB) for input signal of 1 GHz at 4 GS/s in simulation of FFT analysis.

Evaluating and debugging solar panel-driven systems is a cumbersome process. The system must be deployed in the wild, software and hardware bugs identified remotely, and the development cycle must be repeated to build a robust system. Emulation platforms for solar panels offer a plausible remedy, however, existing systems have narrow operating range and are not portable. To address these shortcomings, we design, implement, and evaluate the SunaPlayer, a solar panel emulation platform that supports a wide operating current range (430 micro-amps to 1.89 amps) and voltage range (0.02 V to 9.8 V), and can be powered using batteries. SunaPlayer uses a high gain analog device, a PNP darlington transistor, a multi-scale driving and measurement circuit, and a novel state machine based proportional-integral-differential controller to build an accurate non-linear model of the solar panel. We have implemented a fully functional SunaPlayer prototype, and demonstrate that it can emulate a wide range of solar panels with high accuracy, low latency, high sensitivity, and low power consumption. The design methodology for the SunaPlayer can be used to build systems that model hard to emulate non-linear devices.

A soft-switching DC-DC converter with secondary-side phase-shift control strategy is proposed for applications requiring wide voltage range and isolated step-down power conversion such as battery charger. Two transformers and a three-leg hybrid rectifier (one MOSFET-leg and two diode-legs) are employed. The primary windings of the two transformers are in-series and the secondary windings are in parallel. Zero voltage switching is achieved for both the primary- and secondary-side power MOSFETs while zero current switching is achieved for the secondary-side diodes in a wide load range. Leakage inductance of the transformers is utilized for power transferring. The voltage stresses of all the devices are clamped automatically. Besides, the converter can operates in the buck, balance and boost modes to achieve a relatively wide input or output voltage range. The secondary-side rectifier can be extended to multiple transformers configuration for high step-down applications. The operation principles are analyzed and experimental results of a 1-kW 100-kHz prototype are provided to verify the effectiveness of the proposed converter.