A novel pseudo random bit generator for cryptography applications

Security and privacy problems in communication systems and social media platforms where digital image/video are shared almost always, have attracted researchers interest on information security. Starting from this point of view, a novel one-dimensional chaotic maps based pseudo random bit generator is proposed to make a significant contribution to the literature about protection of personal data in any network. Electronic circuit realizations of Logistic and Tent maps as entropy source are designed on Orcad-Pspice environment and state variables are inputted to novel post-processor algorithm. The rest of main blocks of proposed pseudo random bit generator design are built up fixed-point binary conversion algorithm, XOR processor and H function post-processor. The generated pseudo random bit series are tested by using NIST 800.22 statistical test suite and applied to color image encryption in order to show the effectiveness of proposed design. Cryptanalysis processes such as histogram, NPCR-UACI and correlation analysis are demonstrated. Analysis results show that the proposed design can be used successfully in many secure communication and media transmission applications.

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (<13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

There is a close relationship between encryption and randomness. The security of encryption algorithms usually depends on the random choice of keys and bit sequences. A famous example is Shannon’s result. Ciphers with perfect secrecy require randomly chosen key strings, which are of the same length as the encrypted message. In Chapter 9, we will study the classical Shannon approach to provable security, together with more recent notions of security. One main problem is that truly random bit sequences of sufficient length are not available in most practical situations. Therefore, one works with pseudorandom bit sequences. They appear to be random, but actually they are generated by an algorithm. Such algorithms are called pseudorandom bit generators. They output, given a short random input value (called the seed), a long pseudorandom bit sequence. Classical techniques for the generation of pseudorandom bits or numbers (see [Knuth98]) yield well-distributed sequences. Therefore, they are well-suited for Monte Carlo simulations. However, they are often cryptographically insecure. For example, in linear congruential pseudorandom number generators or linear feedback shift registers (see, e.g., [MenOorVan96]), the secret parameters and hence the complete pseudorandom sequence can be efficiently computed from a small number of outputs.

A novel method to combine encryption and channel coding in such a way as to get increased security without any additional complexity is presented in this paper. A secure communication system usually consists of an encryption block followed by the channel coder. The encryption block here is a Shrinking generator which is a Linear Feedback Shift Register (LFSR) based stream cipher system. The channel coding technique used is Turbo codes or Low Density Parity Check Codes (LDPC) that performs very well and provides results near Shannon's Limit. Controlled randomness using Pseudo Random Bit Sequence (PRBS) generator is incorporated during encoding of these codes to provide additional level of security in the system without any additional complexity. To achieve optimum decoding, soft decision decoding algorithms are used rather than hard decisions. Bit Error Rate (BER) performance of the proposed channel coders with keyed randomness is well analyzed for intended and un-intended users. Security of the system is analyzed by mounting Improved Linear Consistency Attack and the results show that a significant increase in security is achieved in a stream cipher based secure communication system without any additional increase in complexity by introducing security in channel coding.

Random number generators represent basic cryptographic primitives. They are widely used in modern security schemes including security protocols, computer security and password sources. In some algorithms (e.g. DSA) or protocols (e.g. zero-knowledge), random numbers are intrinsic to the computation [3]. In all these applications, strength of security depends greatly on the quality of randomness of the source. Pseudo random number generators (PRNGs) play an important role in cryptographic applications, as the security of these systems depends on the assumption that future values in the random sequence can be unpredictable. A linear feedback shift register (LFSR), in effect, implements a binary polynomial generator. These generators find common use for PRNGs. However, the random sequence generated by LFSR can not guarantee the unpredictability in secure system. We have used genetic algorithm to improve LFSR and proposed a novel random number generator with complex architecture and longer period.

SummaryThis paper presents the design and implementation of an integrated architecture for embedding security into quasi‐cyclic (QC) low‐density parity‐check (LDPC) code–based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standardS‐boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource‐constrained applications.

Generation of pseudorandom binary sequences by means of linear feedback shift registers (LFSRs) with dynamic feedback

At Indocrypt’2002, a new pseudorandom generator based on linear feedback shift register (LFSR) and feedback with carry shift registers (FCSR) was proposed by Arnault. And at Indocrypt’2004, Bin Zhang et al. showed that the self-synchronizing stream cipher constructed by Arnault’s pseudorandom generator was extremely weak against a chosen ciphertext attack. In this paper, we show that the synchronizing stream cipher constructed by Arnault’s pseudorandom generator bear good immunities to the attack proposed by Bin Zhang et al., but can not resist the LFSRization attack proposed by Martin Hell and Thomas Johansson. Then we propose a modification to the synchronizing stream cipher, and show that it inherits of the nice statistical properties of the pseudorandom generator and provided a resistant to the known attacks. The new architecture still has high throughput and low implementation cost.

Pseudo Random Bit and Number Generator (PRB/NG) circuits being very widely used for security, compressive sensing and diverse other applications in telecommunications are studies in different aspects in the laboratory of Computer-aided Design in Telecommunications in Technical University-Sofia. Some results of this study are published in [1] where tests for randomness from the National Institute of Standards and Technology (NIST) suit are applied on commonly used PRB/NGs. Other aspects of the PRB/NG circuits study is their power consumption in the aim of green communications as noticed in [2,3] and the concern about low power consuming devices for Internet of Things’ (IoT) applications. A recent research, described in [4] has confirmed the strong influence of VHDL codes of a circuit design from a given specification and it’s illustrated for a 4-bit comparator circuit. This paper considers power consumption estimation results for a set of PRB/NG circuits in the aim to add power consumption constraints at the design stage for such circuits and to help optimal design selection with minimal power consumption for a given application. The PRB/NG circuits are implemented on XILINX FPGA devices and they are simulated with the Power analyzer option of VIVADO tool and XPE. The approach proposed can be useful for other classes of communication circuits.

This paper explores the dynamic concept of digital signal processing (DSP), with a focus on the design and implementation of Infinite Impulse Response (IIR) bandpass filters. Emphasizing their pivotal role in diverse technological applications, the manuscript details a sophisticated RF signal processing setup integrating sine generators, Pseudo Random Bit Generator (PRBS), and optical modulation. The subsequent introduction of a Bandpass Bessel Filter, meticulously centered at 7 GHz, with a bandwidth of 1.25 GHz, is examined through RF spectrum analyzer and compared with different types of bandpass filters. Results confirm the filter's efficacy in isolating the desired frequency range, thereby refining the modulated RF signal. The integration of such filters is underscored for its impact on signal integrity and reliability, offering valuable contributions to the ongoing dialogue in DSP.

In order to scale down a circuit size for hardware realization of neural network systems, there are many researches on a conventional pulse model neuron, in which, a conventional numerical calculation is replaced by a stochastic calculation. In the conventional stochastic calculation, LFSR (linear feedback shift register) has been used as a random number generator. In general, a good randomness is required for an exact calculation result. However, since the random numbers which are generated by LFSR is lacking in the randomness, there is a problem which affects an accuracy of the conventional stochastic calculation which uses LFSR for generating the random numbers. In our work, in order to improve the accuracy of the conventional stochastic calculation, we propose to use GLFSR (generalized-LFSR) which generates the random numbers which are rich in randomness as the random number generator for the stochastic calculation. The accuracy of the stochastic calculation is also evaluated using a standard deviation value (SD) and a maximum error. As a result, the proposed stochastic calculation which using GLFSR as the random number generator shows a highest accuracy of the calculation result.

Transmission of images on the network is considered insecure which has security-related issues. In this paper, to provide security to digital images, an encryption system that uses four chaotic maps for binary key sequence generation is proposed. The system consists of stages namely, confusion, generation of random binary chaotic key sequence, pseudo-random number generation (RN), and diffusion. Keys for encryption are chosen randomly based on a pseudo random generator from the selected chaotic maps by the linear feedback shift register (LFSR). The algorithm achieves good results in terms of NPCR, UACI, and entropy values. The developed cryptosystem resists differential attacks, is sensitive to minor alterations in the keys, and has a large key space.

Random number generator (RNG) is a fundamental element in modern cryptography. If the quality of the outputs generated by RNGs is not as well as expected, the cryptographic applications which use the random number service are vulnerable to security threats. In reality, the entropy source of RNGs could be impressible by the changes of environmental factors, resulting in defects in the generated data, such as poor statistical properties. Thus, RNG is generally designed with a preset post-processing module to improve the quality of the output sequences. Linear feedback shift register (LFSR) is one of the frequently used methods for post-processing thanks to the characteristic of simplicity and no reduction in output throughput. However, we point out that even if the statistical properties of the outputs of the entropy source are extremely poor, the sequences processed by LFSR can still pass the statistical test. This undoubtedly increases the security risks in the usage of RNGs. In this work, we propose a distinguisher for the RNGs with LFSR post-processing for the first time. The distinguisher can be used to detect the RNGs with LFSR post processing, and we theoretically prove the sequences before processing can be recovered. On this basis, we design a new statistical test via combining the distinguisher with the Frequency Test in the NIST test suite. The experimental results show that if the sequence is biased before being processed by LFSR, our proposed method can detect it, but the NIST SP 800-22 Test Suite cannot.KeywordsRandom number generatorLFSRPost-processingDistinguisherRandomness test

During testing, the power dissipation is more than normal working. Among many reasons, one reason is due to a lot of transitions occur between bits of test patterns generated. The work advised here has a low power pattern generator for a built-in-self-test (BIST) design. The proposed design is a low power, improved version of a conventional linear feedback shift register (LFSR). The proposed designed named half-start-half-stop pattern generator (2HS-PG) is comprised of conventional LFSR, redesigned with add-on circuitry which brings down the total number of switching between the bits, results in low switching power during testing. Implementation of both conventional LFSR and 2HS-PG design are done in Cadence Genus tool, using 90 nm standard cell technology library and simulation is done in Xilinx ISE tool. Simulation result and analysis shows that more than 30% dynamic power reduction, when patterns are generated using proposed pattern generator.KeywordsBISTLFSRBit-swapping lFSR (BS-LFSR)Pseudo random pattern generator (PRPG)Low power pattern generator