FPGA implementation of highly secure, hardware‐efficient QC‐LDPC code–based nonlinear cryptosystem for wireless sensor networks

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

In this paper, a novel pseudo random bit generator is presented. It exhibits better inviolability properties, with respect to the traditional one, and it can be efficiently used in cryptography applications where high security is required. The proposed circuit is based on the classical linear feedback shift register (LFSR) with the feedback network dynamically modified. It has been evaluated with the most common randomness tests, giving excellent results. Moreover, the main statistical properties of the novel generator have been compared with those of a LFSR of equivalent length. The results have shown an equivalent performance of the circuits under comparison.

Multiple input multiple output (MIMO) system is one of the most promising wireless technologies that can achieve wide coverage, high throughput and improved reliability. Low density parity check (LDPC) codes can achieve capacity near Shannon's limit with good error correcting performance. In this paper, we combined LDPC codes with orthogonal space time block codes (OSTBC) in MIMO systems. The performance of LDPC codes depends on the structure of the parity check matrix and decoding algorithms. In this paper, we analyzed the bit-error rate (BER) performance of different LDPC codes like Quasi Cyclic (QC) and random which differs in their parity check matrix structures. For low complexity decoding, log domain Sum Product Algorithm (log-SPA) is used which has messages in the form of log-likelihood ratios (LLR). Further, the approximate BER expressions are derived and verified for above mentioned system with different antenna configurations.

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

It is shown how to construct a general linear hybrid cellular automaton (CA) such that it has a maximum length cycle, and how the aliasing properties of such automata compare with linear feedback shift registers (LFSRs) when used as signature analyzers. The construction is accomplished by formally demonstrating the isomorphism which binds this kind of CA to the LFSRs. Consequently, these CAs can be analyzed as linear machines. Linear algebraic techniques are then applied appropriately for the transformations, and a useful search algorithm is developed which, given an irreducible characteristic polynomial, finds a corresponding linear hybrid automaton. Such CAs are tabulated for all irreducible and primitive polynomials up to degree 16, plus a selection of others of higher degree. The behavior of a linear hybrid CA and that of its corresponding LFSR are similar-that is, they have the same cycle structure and only relabel the states. The aliasing properties, when they are used as signature analyzers, remain unchanged.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (&#60;13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

In order to scale down a circuit size for hardware realization of neural network systems, there are many researches on a conventional pulse model neuron, in which, a conventional numerical calculation is replaced by a stochastic calculation. In the conventional stochastic calculation, LFSR (linear feedback shift register) has been used as a random number generator. In general, a good randomness is required for an exact calculation result. However, since the random numbers which are generated by LFSR is lacking in the randomness, there is a problem which affects an accuracy of the conventional stochastic calculation which uses LFSR for generating the random numbers. In our work, in order to improve the accuracy of the conventional stochastic calculation, we propose to use GLFSR (generalized-LFSR) which generates the random numbers which are rich in randomness as the random number generator for the stochastic calculation. The accuracy of the stochastic calculation is also evaluated using a standard deviation value (SD) and a maximum error. As a result, the proposed stochastic calculation which using GLFSR as the random number generator shows a highest accuracy of the calculation result.

Monte Carlo (MC) method is widely used in resolving mathematical problems that are too complicated to solve analytically. The method involves with sampling process of the random numbers and probability to estimate the result. As MC method depending on a large number of good quality random numbers to produce a high accuracy result, developing a good random number generator (RNG) is vital. Most of random number generators are developed in software based, with the improvement of Field Programmable Gate Arrays (FPGA) density and speed in recent days, implementing random number generator (RNG) directly into hardware is feasible. Random Walk on the Boundary (WOB) is one of MC methods that applied to calculate the unit cube capacitance. The unique requirement of this method is the random numbers produced by RNG must fall within the Gaussian distribution and the maximum decimal values in the range of [0, 1]. Thus, in this paper we presented a novel hardware RNG for Random WOB method to calculate unit cube capacitance in FPGA. The RNG is implemented in floating-point base, using the combination of Cellular Automata Shift Register (CASR) and Linear Feedback Shift Register (LFSR) then channeled through Box-Muller transformation. There is linear approximation in computing logarithmic function applied in Box-Muller transformation. Based on statistical tests, the random numbers generated is nearly 97.5% resembling the standard normal distribution.

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

There are several attempts to use chaotic nonlinear maps for random number generation. Theoretically, some chaotic maps can produce balanced and i.i.d. (independent and identically distributed) binary sequences. Also, chaotic binary sequences with prescribed auto-correlations can be generated. However, it is difficult to generate aperiodic sequences with prescribed auto-correlation properties by analog circuits or digital circuits only. In this paper, we propose a simple post-processing by linear feedback shift registers for generating random bit sequences with prescribed (positive/negative) auto-correlations. We perform some numerical experiments for investigating the effects of the proposed post-processing.

The stream cipher, a type of secret‐key cipher, gives the key to a pseudorandom number generator and generates a pseudorandom sequence called the key sequence, and generates the ciphertext sequence taking the exclusive‐or of this sequence and the plaintext sequence. A nonlinear combiner generator is a type of pseudorandom number generator used by stream ciphers and is configured from multiple linear‐feedback shift registers (LFSRs) and one nonlinear function. A correlation attack is a method for attacking this type of pseudorandom number generator. The correlation between the output sequence of an LFSR and the key sequence is used to estimate the initial state of the LFSR. However, a conventional attack method attacks a single LFSR and is used only to estimate a portion of the multidimensional correlations of the multiple LFSR sequences and the key sequence. Therefore, we propose an algorithm that improves the attack method using the belief propagation (BP) algorithm of Mihaljević and colleagues and simultaneously attacks multiple LFSRs using the multidimensional correlation. By increasing the information used in the estimation, an improvement in the decoding success rate is expected. In addition, the computational load of the estimation increases, but this increase can be suppressed by an approximation based on the parallel BP algorithm. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(4): 9 – 17, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20270

Random number generators represent basic cryptographic primitives. They are widely used in modern security schemes including security protocols, computer security and password sources. In some algorithms (e.g. DSA) or protocols (e.g. zero-knowledge), random numbers are intrinsic to the computation [3]. In all these applications, strength of security depends greatly on the quality of randomness of the source. Pseudo random number generators (PRNGs) play an important role in cryptographic applications, as the security of these systems depends on the assumption that future values in the random sequence can be unpredictable. A linear feedback shift register (LFSR), in effect, implements a binary polynomial generator. These generators find common use for PRNGs. However, the random sequence generated by LFSR can not guarantee the unpredictability in secure system. We have used genetic algorithm to improve LFSR and proposed a novel random number generator with complex architecture and longer period.

A novel method to combine encryption and channel coding in such a way as to get increased security without any additional complexity is presented in this paper. A secure communication system usually consists of an encryption block followed by the channel coder. The encryption block here is a Shrinking generator which is a Linear Feedback Shift Register (LFSR) based stream cipher system. The channel coding technique used is Turbo codes or Low Density Parity Check Codes (LDPC) that performs very well and provides results near Shannon's Limit. Controlled randomness using Pseudo Random Bit Sequence (PRBS) generator is incorporated during encoding of these codes to provide additional level of security in the system without any additional complexity. To achieve optimum decoding, soft decision decoding algorithms are used rather than hard decisions. Bit Error Rate (BER) performance of the proposed channel coders with keyed randomness is well analyzed for intended and un-intended users. Security of the system is analyzed by mounting Improved Linear Consistency Attack and the results show that a significant increase in security is achieved in a stream cipher based secure communication system without any additional increase in complexity by introducing security in channel coding.

본 논문에서는 OFDM 시스템에서 고속 처리와 성능 향상을 위한 LDPC 코드 기반 결정 궤환 등화기(Decision Feedback Equalizer: DFE)를 제안한다. LDPC 코드는 우수한 오류 정정 능력과 Shannon의 채널 용량에 근접하는 성능을 갖는다. 그러나, 많은 parity 검사 행렬과 반복 횟수를 가진다는 단점이 있다. 제안된 시스템에서는 판정된 신호와 복호기 사이의 신호의 MSE(Mean Square Error)를 등화기로 피드백한다. 이러한 방법을 사용하면 추정된 채널 응답을 보정해 주기 때문에 성능을 향상시킬 수 있다. 또한, 동일한 성능에서 피드백이 포함되지 않은 시스템보다 낮은 반복 횟수를 갖기 때문에 시스템의 복잡도를 줄일 수 있다. 시뮬레이션을 통해 다중 경로 채널에서 CFO(Carrier Frequency Offset)와 위상 잡음이 고려된 OFDM 시스템의 성능을 평가하여 제안 시스템의 우수성을 보인다. In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.