A study on random bit sequences with prescribed auto-correlations by post-processing using linear feedback shift registers

In stream cipher systems, random key sequence generation is the primary task. The concept of chaotic systems can be considered in generating a random key sequence due to its inherent randomness property. Though the chaotic real sequences are random, the randomness will be lost after converting them to binary sequences. In this context, the authors propose a technique which uses a non‐linear feedback system to enhance the randomness of the binary sequences. In this work, three binary chaotic sequences using a logistic map are generated with three different initial conditions and each real value of the chaotic sequence is converted to ‘k’ bit binary value using a thresholding function. Some of the resulting sequences are not random. Hence, in this article a non‐linear structure is used to make the resulting sequence random. Here, a non‐linear function similar to the structure of the Simplified Data Encryption Standard is used to generate a sequence using two non‐random chaotic binary sequences. The resulting sequence is XORed with another non‐random chaotic binary sequence to get a random sequence. Sequences obtained from this nonlinear system are subjected to randomness tests and the results indicate that the sequences pass all the randomness tests. Hence, the sequences qualify as random key sequences, which can be used in a stream cipher based system to encrypt the data samples like audio, image, video, and so forth.

Transmission of images on the network is considered insecure which has security-related issues. In this paper, to provide security to digital images, an encryption system that uses four chaotic maps for binary key sequence generation is proposed. The system consists of stages namely, confusion, generation of random binary chaotic key sequence, pseudo-random number generation (RN), and diffusion. Keys for encryption are chosen randomly based on a pseudo random generator from the selected chaotic maps by the linear feedback shift register (LFSR). The algorithm achieves good results in terms of NPCR, UACI, and entropy values. The developed cryptosystem resists differential attacks, is sensitive to minor alterations in the keys, and has a large key space.

Communication security that depends on chaos can be considered as a new approach which provides protection and security of communications and maintains confidentiality because Chaos theory can be implemented in cryptosystem successfully. A stream cipher, on the other hand, is a type of symmetric cryptosystem in which the plaintext is divided into small entities known as characters. The key in stream cipher is typically generated by a random bit generator. Many key stream generators employ linear feedback shift registers (LFSRs). LFSR systems are made up of a group of LFSR units and a combining function (CF) unit. The plaintext is encrypted one bit at a time. The key is fed into a random bit generator, which produces a long series of binary signals. This "key-stream" k is then combined with plaintext m, typically via a bit-wise XOR (Exclusive-OR modulo 2 addition), to produce the ciphertext stream, which employs the same random bit generator and seed. In this paper we will introduce a new stream cipher keygenerator which using a hybrid between chaotic and combination of Linear Feedback Shift Registers (LFSR's). The proposed generator can be used to protect different types of data files (text, image, audio and video). Many kinds of tests are applied to specifying the goodness of the proposed keygenerator. The results of testing prove the efficiency of the suggested system.

The current information age demands enormous opportunities, where, the sensitive data and information is being exchanged, analyzed and made use of. It has led to several concerns and challenges, mainly in the areas of information privacy, authentication and integrity. This concern, attracted cryptographers to device more effective methodologies and algorithms to ensure better protection to sensitive information. In this context, the application of chaotic based systems is considered to design a pseudorandom sequence generator, which is used as a key stream generator in the additive Stream Cipher system. Chaotic map is a mathematic function that generates highly nonlinear and random real sequence which is very sensitive to initial conditions. In this view, this work focusses on the study of Logistic map, considered from a bunch of various Chaotic functions available [1], [2]. Chaotic real sequence is binarized using a new binarization algorithm using Linear Feedback Shift Register (LFSR), which is designed in such a way that the randomness of Chaotic real sequence is not affected as far as possible. Using Logistic map, about 50 sequences are generated each of length ≥ 106. To ensure the randomness of binary sequences, NIST(National Institute of Standards and Technology) test is used. It is observed that, all the sequences have strictly passed most of the NIST tests with an average passing proportion ≥ 0.87. These sequences are used as key sequences in image encryption and decryption. It is interesting to observe that, encrypted image does not contain any residual information. This result is cross verified by plotting the Histogram, computing the Correlation coefficient and Entropy of the output images. It is observed that, Histograms are almost flat indicating the equiprobable distribution of pixels. Also, Entropy of the encrypted image is close to 8 and Correlation coefficient value is very negligible indicating that neighboring pixels are heavily uncorrelated. As the key sequence based on Chaotic functions is sensitive to initial conditions, the sequence generated will be highly nonlinear and random which encourages one to use in cryptographic applications.

The chaotic functions and cyclic elliptic curves (CEC) has attracted many researchers, especially cryptographers, since decades. As CEC and chaotic functions meet the requirements of the cryptography, they are widely used either in key sequence generation or encryption/decryption process. Since in symmetric key encryption, stream ciphers need a large key sequence to encrypt/decrypt the information, authors propose a hybrid model to generate pseudo random sequence using CEC and logistic map. The hybrid model is developed using CEC points over and an one‐dimensional logistic map. In the proposed system, binary chaotic sequence and CEC points are given to AES S‐box to get two random sequences separately. Byte wise parity is computed for both the sequences. Based on the parity of both the bytes, one of the byte is left shifted and the other is right shifted by two positions in a circular manner. Later, both the bytes are combined using the XOR operation to get the random binary sequence. The generated sequences are analysed for randomness using various test suites like NIST, Correlation, FIPS, and TestU01. It has been observed that all the sequences pass the randomness tests. Using additive stream cipher, image encryption is implemented by considering the generated sequence as key sequence. The performance evaluation and security analysis of the encryption process is conducted. The results obtained for the proposed system indicate that the system is robust to withstand many cryptanalytic attacks.

본 논문에서는 1차원 혼돈맵들 중의 하나인 톱니맵을 16비트의 유한정밀도로 이산화시켜 설계하였고, 이 이산화된 톱니맵을 사용한 혼돈 2진 순서 발생기의 회로도도 제시하였다. 설계된 혼돈맵의 실제 구현은 이산화된 진리표로부터 얻어진 출력변수의 간략화된 부울함수에 따른 입력선과 출력선들의 정확한 연결에 의해 실현하였다. 최대길이를 발생시키는 선형궤환이동레지스터(mLFSR)에 의해 발생되는 난수성 2진 출력 순서들을 이산화된 톱니맵의 입력순서로 사용함으로써 결과적으로 최소 16배 더 긴 주기를 갖는 혼돈 2진 순서들을 발생시켰다. The discretized saw-tooth map with the 16-bit finite precision which is one of the 1-dimensional chaotic maps is designed, and the circuit of chaotic binary sequence generator using the discretized saw-tooth map is presented also in this brief. The real implementation of designed chaotic map is accomplished by connecting the input and output lines exactly according to the simplified Boolean functions of output variables obtained from truth table which is discretized. The random binary output sequences generated by mLFSR generator were used for the inputs of descretized saw-tooth map, and, by the descretized map, chaotic binary sequence which has more long period of 16 times minimally is generated as a results.

Linear feedback shift registers (LFSRs) are essential components of communications systems such as pseudo random bit sequence (PRBS) generators, convolutional encoders, scramblers and randomizers [1, 2]. Fig.1 (left) shows a LFSR scheme in which the XOR gate is operated among two tapped bits i and i+k within the shift register. The result bit is fed to the shift register at the last position (n) and the sequence in the register is 1-bit shifted as well. The experimental setup for demonstrating an all-optical LFSR is shown in Fig.1 (middle). The main components of the scheme are an optical buffer [3], a bit selecting circuit, and a XOR gate. The data vector (A) is generated by modulating the continuous wave (CW) λ s with a 10Gbps non-return-to-zero (NRZ) electrical pattern whose period is T P =33.3168µs. Only 5 bits are used as the initial sequence for the shift register. The travelling time of the packet in the buffer is T L =1.85 µs, meaning that up to 18 round trips can be accommodated by the pattern's period T P but one of those should be preserved for erasing the buffer before it is fetched a new sequence. The initial sequence enters the buffer as well as propagates directly to the bit selecting circuit. Every round trip, a new sequence as a replica of the previous one plus the feedback bit comes out. At the last round trip, a pump signal inserted into the buffer through the circulator will strongly reduce the gain of the semiconductor optical amplifier (SOA). Both the circulating packet and the accumulating in-band amplified spontaneous emission (ASE) noise will be suppressed. The buffer is now completely cleaned for a new cycle. The first and the last bits of the 1-bit shifted sequence are selected for the XOR operation. Referring to Fig.1 (left), i=1 and k=4, n=5. With this setup, the bit selecting circuit requires 2 clock signals (C) for tap the proper bits from the incoming sequence. The sampling process is done by exploiting four-wave-mixing (FWM) in a 250m-long highly nonlinear fiber (HNLF). Since at every round trip the sequence must be 1-bit shifted, the sampling clocks must be accordingly delayed for 1 bit, resulting the clock period of T C =T L +T B where T B =100ps is the bit time. The outputs of the bit selecting circuit are fed as pump signals to port a and d of a SOA Mach Zehnder interferometer (MZI). They are synchronized with a clock at λ s used as the probe signal (F) at port b. The output of the XOR gate is then fed back into the buffer. The feedback bit should be precisely allocated at the end of the packet circulating inside the buffer, meaning that the feedback time should be T F =T L +T B +T seq in which T seq is the original sequence duration and equal to 500ps in our setup. Fig.1 (right) depicts the results at the 10th round trip for two different input initial sequences (10001) and (10011) taken at point (B). The equalization between bits in the sequence and the quality of the pulses is strongly limited by the accumulating ASE noise inside the buffer, the long fiber-based structure and the bit's polarization. The fiber-based setup also causes misalignment between the clocks, spoils the essential synchronism and degrades the performance of the FWM and the XOR operation. One possible solution for solving all of these problems and hence improving the performance is the integration approach. The bit selection could be implemented exploiting nonlinear effects into an SOA or a periodic-poled lithium niobate (PPLN) instead of using a long HLNF. Moreover the extinction ratio of the pulses at the SOA-MZI XOR output (<13.5dB) could be improved, e.g. with a saturable absorber at its output, thus increasing the number of allowed round trips into the shift register and reducing the noise on the final bit sequence.

Chaotic sequences have good correlation properties and they can be used as address sequences in Spread Spectrum Communication. Chaotic functions are highly sensitive to initial condition and exhibit non-linear behavior. In Chaotic spread spectrum communication systems, different user may be assigned different sequences generated with different initial conditions. Set of binary sequences with good pair wise cross- correlation property finds applications in Direct Sequence- Code Division Multiple Access (DS-CDMA) systems. Security in Direct Sequence-Code Division Multiple Access systems is relatively limited. To enhance security in Direct Sequence- Code Division Multiple Access systems, chaotic sequences are generated. In this paper we analyze the generation of chaotic binary sequences and study of auto correlation and cross correlation properties.

In this paper, a novel pseudo random bit generator is presented. It exhibits better inviolability properties, with respect to the traditional one, and it can be efficiently used in cryptography applications where high security is required. The proposed circuit is based on the classical linear feedback shift register (LFSR) with the feedback network dynamically modified. It has been evaluated with the most common randomness tests, giving excellent results. Moreover, the main statistical properties of the novel generator have been compared with those of a LFSR of equivalent length. The results have shown an equivalent performance of the circuits under comparison.

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

In today’s world of critical global connectivity, satellite communication plays a vital role for businesses, governments, and individuals. Key applications, including climate change monitoring, military surveillance, and real-time event broadcasting, heavily rely on transmitting image data rather than text. As a result, ensuring the secure transmission of images through efficient and robust encryption techniques has become a focal point of interest for both academia and industry. Image encryption is essential for securing sensitive visual data, protecting privacy, and making certain that only authorized users are able to access the required content. It prevents unauthorized access, tampering, and misuse of images, which is crucial for confidential and secure communications. The work in this paper develops a satellite image encryption scheme that employs a novel 1D Cosine Sinusoidal Chaotic (1DCSC) map, and two earlier proposed Sine-Tangent Chaotic (STC) and Improved Cosine Fractional Chaotic (ICFCM) maps, in conjunction with Deoxyribonucleic Acid (DNA) operations. The proposed scheme encrypts a given input image in four steps. In the initial step, 384-bit shared key and a 128-bit initial vector are used to create three different keys. In step two, three different chaotic sequences are produced using these keys and 1DCSC, STC, and ICFCM maps. These chaotic sequences chosen randomly to encrypt red, blue or green components of the given input image. In step three, these three chaotic sequences and the three components of the input image are DNA encoded. In the final step, DNA XOR based diffusion operation is applied between these DNA-encoded color image components and DNA encoded chaotic sequences to create green, red, and blue components of the cipher image. The proposed scheme obtains entropy value 7.9997, Unified Average Changing Intensity (UACI) value 33.32, and Number of Pixels Change Rate (NPCR) value 99.67%.

A novel method to combine encryption and channel coding in such a way as to get increased security without any additional complexity is presented in this paper. A secure communication system usually consists of an encryption block followed by the channel coder. The encryption block here is a Shrinking generator which is a Linear Feedback Shift Register (LFSR) based stream cipher system. The channel coding technique used is Turbo codes or Low Density Parity Check Codes (LDPC) that performs very well and provides results near Shannon's Limit. Controlled randomness using Pseudo Random Bit Sequence (PRBS) generator is incorporated during encoding of these codes to provide additional level of security in the system without any additional complexity. To achieve optimum decoding, soft decision decoding algorithms are used rather than hard decisions. Bit Error Rate (BER) performance of the proposed channel coders with keyed randomness is well analyzed for intended and un-intended users. Security of the system is analyzed by mounting Improved Linear Consistency Attack and the results show that a significant increase in security is achieved in a stream cipher based secure communication system without any additional increase in complexity by introducing security in channel coding.

There is a close relationship between encryption and randomness. The security of encryption algorithms usually depends on the random choice of keys and bit sequences. A famous example is Shannon’s result. Ciphers with perfect secrecy require randomly chosen key strings, which are of the same length as the encrypted message. In Chapter 9, we will study the classical Shannon approach to provable security, together with more recent notions of security. One main problem is that truly random bit sequences of sufficient length are not available in most practical situations. Therefore, one works with pseudorandom bit sequences. They appear to be random, but actually they are generated by an algorithm. Such algorithms are called pseudorandom bit generators. They output, given a short random input value (called the seed), a long pseudorandom bit sequence. Classical techniques for the generation of pseudorandom bits or numbers (see [Knuth98]) yield well-distributed sequences. Therefore, they are well-suited for Monte Carlo simulations. However, they are often cryptographically insecure. For example, in linear congruential pseudorandom number generators or linear feedback shift registers (see, e.g., [MenOorVan96]), the secret parameters and hence the complete pseudorandom sequence can be efficiently computed from a small number of outputs.

In this paper, we propose a new HW (hardware)-based truly random bit sequence generation method and show its experimental results. The method can be used in a personal computer and ensures the randomness of the obtained bit sequence. We can generate a HW-based truly random bit sequence at high speed based on the realtime clock deviation which is unpredictable. Also, the random bit sequences generated by this method have passed ldquoA Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications (NIST Special Publication 800-22)rdquo with appropriate parameters. The proposed random bit sequence generation method can be used in many cryptographic applications.

Although discrete-time chaotic-map TRNGs, in principle, are capable of generating unbiased and uncorrelated random bits, implementation variations deteriorate the quality of the output sequence as a result of variation of the chaotic map parameters (which result in a non-ideal map). In this paper, we introduce an analytical technique to investigate the impact of process variations on the randomness of the output sequence generated using tent map-based discrete-time chaotic map truly random number generators (TRNGs). We validate our results against the probability density function (pdf) estimated using extensive Monte-Carlo simulations applied to the non-ideal map characteristics. The simulation results suggest that the estimation of pdf using our simplified theoretical method is in good agreement with that of the Monte-Carlo simulations. Finally, the quality of the random bits have also been evaluated using the entropy measure.