A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors

This thesis has been carried out in the field of Computer Networks. We have looked after two challenging and popular multimedia applications over the Internet, namely Real-time Multimedia Applications, considering Multimedia Conferencing and Voice over IP (VoIP) services in general, and Content-Oriented Applications, that are multimedia web services such as User Generated Contents (UGC) platforms and Online Social Networks. We have conducted our studies starting from a thorough review of both functional and non-functional issues related to the above mentioned application families. We first consider a number of different facets of Real-time Multimedia Applications, dealing with architectural, performance and security issues. We embrace an engineering approach, by involving modeling, implementation and simulation. We try and adhere to standard architectures by also actively contributing to them, arriving at the definition and completion of a fullyfledged standards-compliant web conferencing platform. We propose original contributions to face performance and security issues. With respect to the former aspect, we address scalability and performance analysis by leveraging formal methods. As to the latter point, we design an effective profiling system for VoIP users which is able to detect an interesting class of VoIP threats represented by “social” attacks. In the second part of the thesis, we focus on Content-Oriented Applications, once again basing our work on a study of current architectural and performance challenges. We propose a framework for the performance optimization of content-delivery based on the awareness of the contents to be delivered, as well as of the users’ behavior in terms of mobility, request patterns and content preferences.

We present ASDSP (application-specific digital signal processor) instructions and their hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly within two cycles. The proposed architecture employs a data processing unit (DPU) supporting the instructions and an FFT address generation unit (FAGU) automatically calculating the butterfly input and output data addresses. The proposed DPU has a smaller area than commercial DSP chips. Moreover, the number of FFT computation cycles is reduced by the proposed FAGU. The architecture has been modeled by the VHDL. We have used the UMC 0.25/spl square/standard cell library for logic synthesis. Performance comparisons show that the number of execution cycles is reduced over 10% and the size of the DPU decreases about 30% compared with Carmel DSP.

System-level designers typically rely on white-box detailed descriptions of embedded systems in order to perform their design choices and optimisations. The white-box approach assumes that the complexity of the system can be managed by decomposing the global system into a set of simple and well-described components. This assumption is generally not true when non-linear interactions happen between the different subsystems. This paper explores, as an alternative, a black-box modelling methodology based on intelligent data analysis in order to support system-level designers in characterising the performance of embedded applications. The rationale behind this approach is that nowadays the designer can easily store large amount of data related to the system, and consequently discover relevant information by analysing them in a black-box fashion. As a case study, we address the performance modelling of software applications running on an embedded microprocessor. We introduce a data analysis method which, on the basis of a high-level characterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on a embedded processor. We propose the adoption of a local learning technique (lazy learning), which proved already to be effective in previous works, to model the unknown input/output relation between the hardware/software parameters of the application and the number of execution cycles. Experiments with standard computational code (sorting, mathematical computation) and with a specific streaming algorithm for MPEG variable length decoding are presented to support this claim.

In the past few years, the ubiquity of embedded mobile computing brings about a new challenge for multimedia application. Not only the performance but also the power consumption is vital to the multimedia application because mobile clients are powered by battery. In this paper, we make the detailed power consumption analysis of multimedia applications with two power reduction techniques—ideal clock gating and ideal power gating. Experimental results show the power consumptions can be reduced to 35.22% and 15.68% by ideal clock gating and ideal power gating, respectively. Our primary contributions lie in evaluating the power characteristics of multimedia applications using MediaBench benchmark suite, and evaluating the impact of unideal power reduction techniques on the performance. Such an analysis can help the multimedia applications developers determine the efficient power optimization policy besides the performance optimization. Low-power embedded multimedia applications are promising in the future.

Bytecode folding is an effective technique for speeding up execution in Java virtual machines. This paper investigates a hardware implementation of the aforementioned technique on BlueJEP, a Java embedded processor. Since BlueJEP is a micro-programmed stack machine, we adopt a micro-instruction oriented approach, folding up to four microinstructions (corresponding to up to four bytecodes, on occasion). A variety of processor versions for different subsets of folding patterns are implemented, simulated and synthesized on a Xilinx FPGA. The measurements and results show that, although the number of execution cycles is reduced, the critical path increase leads to a lower performance. Taking into account the device area, we conclude that for our case, adding a second processor may be preferred over hardware folding. In general, we observe that folding efficiency may only be evaluated properly on a real implementation, rather than using theoretical estimates, due to the increased complexity of the hardware.

To manifest anticipatory behaviour that goes beyond simple stimulus-response, classifier systems must evolve internal reasoning processes based on couplings via internal messages. A major challenge that has been encountered in engendering internal reasoning processes in classifier systems has been the discovery and maintenance of long classifier chains. This paper proposes a modified version of the traditional classifier system, called the delayed action classifier system (DACS), devised specifically for learning of anticipatory or predictive behaviour. DACS operates by delaying the action (i.e. posting of messages) of appropriately tagged, matched classifiers by a number of execution cycles which is encoded on the classifier. Since classifier delays are encoded on the classifier genome, a GA is able to explore simultaneously the spaces of actions and delays. Results of experiments comparing DACS to a traditional classifier system in terms of the dynamics of classifier reinforcement and system performance using the bucket brigade are presented and examined. Experiments comparing DACS with a traditional classifier system, which appear encouraging, for a simple prediction problem are described and considered. Areas for further work using the delayed-action classifier notion are suggested and briefly discussed.KeywordsGenetic AlgorithmClassifier SystemTraditional ClassifierMarginal PayoffLetter SequenceThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Smart Access Points on the road for online gaming in vehicular networks

Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized—our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.

Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. We propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce the majority of the conflict cache misses. The focus of this paper is on the formal and heuristic algorithm we use to steer the data layout decisions and the experimental results obtained using a prototype tool. Experiments on real-life demonstrators illustrate that we are able to reduce up to 82 percent of the conflict misses for applications which are already aggressively transformed at source-level. At the same time, we also reduce the off-chip data accesses by up to 78 percent. In addition, we are able to reduce up to 20 percent more conflict misses compared to existing techniques.

Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory

Homomorphic encryption for smart grids has been investigated in many studies. It is possible to estimate the total power consumption in an area without knowing the consumption data of individual households. In the case of demand response (DR), it is important to calculate the total electric power consumption in an area because DR reports are published accordingly to reduce peak power consumption when the demand is high. However, the published data may reveal private information about residents, such as the timings of specific activities (leaving from and returning home), and device details. To overcome this problem, we propose a method specialized to enable energy providers to securely share electric power consumption data. The proposed method uses a self-organizing map (SOM), which is an unsupervised learning method. In order to share power consumption data while preserving privacy, the SOM is shared without the raw data. In this framework, a target accuracy of nearly 3% is achieved, while actual data are not published by any company.

The demand for higher computing power and, thus, more on-chip computing resources; is ever increasing. The size of on-chip cache memory has also been consistently increasing to keep up with developments in implementation technology. However, some applications may not utilize full cache capacity and, on the contrary, require more computing resources. To efficiently utilize silicon real-estate on the chip, we exploit the possibility of using a part of cache memory for computational purposes to strike a balance in the usage of memory and computing resources for various applications. In an earlier part of our work, the idea of adaptive balanced computing (ABC) architecture was evolved, where a module of an L1 data cache is used as a coprocessor controlled by main processor. A part of an L1 data cache is designed as a reconfigurable functional cache (RFC) that can be configured to perform a selective core function in the media application whenever such computing capability is required. ABC architecture provides speedups ranging from 1.04x to 5.0x for various media applications. We show that a reduced number of cache accesses and lesser utilization of other on-chip resources, due to a significant reduction in execution time of application, will result in power savings. For this purpose, we first develops a model to compute the power consumed by the RFC while accelerating the computation of multimedia applications. The results show that up to a 60 percent reduction in power consumption is achieved for MPEG decoding and a reduction in the range of 10 to 20 percent for various other multimedia applications. Besides, beyond the discussions in earlier work on ABC architecture, we present a detailed circuit level implementation of the core functions in the RFC modules. Further, we go much further and study the impact of converting the conventional cache into RFC on both access time and energy consumption. The analysis is performed on a wide spectrum of cache organizations with size varying from 8KB to 256KB for varying set associativity.

Information systems based on the cloud computing model and peer-to-peer (P2P) model are now getting popular. In the cloud computing model, a cloud of servers support thin clients with various types of service like Web pages and databases. On the other hand, every computer is peer and there is no centralized coordinator in the P2P model. It is getting more significant to discuss how to reduce the total electric power consumption of computers in information systems to realize eco-society. In this paper, we consider a Web type of application on P2P overlay networks. First, we discuss a model for showing how much each server peer consumes electric power to perform Web requests from client peers. Then, we discuss algorithms for a client peer to select a server peer in a collection of server peers so that the total power consumption can be reduced while some constraint like deadline one is satisfied. Lastly, we evaluate the algorithms in terms of the total power consumption and throughput compared with traditional round robin algorithms.

Information systems are composed of various types of computers interconnected in networks. In addition, information systems are being shifted from the traditional client-server model to the peer-to-peer (P2P) model. P2P systems are scalable and fully distributed without any centralized coordinator. Here, it is getting more significant to discuss how to reduce the total electric power consumption of computers in addition to developing distributed algorithms to minimize the computation time and memory space. In this paper, we do not discuss microlevel models like the hardware specifications of computers like low-energy CPUs. We rather discuss a macrolevel model to show the relation of the amount of computation and the total power consumption of multiple peer computers to perform Web types of application processes. We also discuss algorithms for allocating a process to a computer so that the deadline constraint is satisfied and the total power consumption is reduced.

Information systems are composed of various types of computers interconnected in networks. In addition, information systems are being shifted from the traditional client-server model to the peer-to-peer (P2P) model. The P2P systems are scalable and fully distributed without any centralized coordination. It is getting more significant to discuss how to reduce the total electric power consumption of computers in information systems in addition to developing distributed algorithms to minimize the computation time. In this paper, we do not discuss the micro level like the hardware specification of each computer. We discuss a model to show the relation of the computation and the total power consumption of multiple peer computers to perform Web types of processes at macro level. We also discuss algorithms for allocating a process to a computer so that the deadline constraint is satisfied and the total power consumption is reduced.