A preliminary version of an optical data-flow architecture

Modern information technologies are increasingly focused on the tasks related to the knowledge processing: intelligent Internet search systems and enterprise resource planning, DataMining and smart home systems, recommender systems for various purposes, etc. Such problems are specified by the availability of large arrays of complexly structured symbol information, a high degree of implicit parallelism, weak formalizability, and a low need for complex arithmetic operations. As a result, the solution of such problems using the off-the-shelf microprocessors is extremely inefficient. One of approaches to solving this problem is to develop a specialized hardware device designed for high-performance symbolic data processing. The proposed logical inference engine is focused on the accelerated method of parallel logical inference that has a high degree of parallelism, and dataflow architecture. The article describes the development of the executive processor of the logical inference engine. The emphasize is placed on the unification unit design. A new method of parallel unification of the predicate pairs is presented. The unification unit logic diagrams developed using the Quartus CAD system have been implemented on FPGA by Altera. The comparative analysis of the sequential and parallel unit implementation on the basis of the experiments performed is provided.

Despite ever increasing computational power, recognition and classification problems remain challenging to solve. Recently advances have been made by the introduction of the new concept of reservoir computing. This is a methodology coming from the field of machine learning and neural networks and has been successfully used in several pattern classification problems, like speech and image recognition. The implementations have so far been in software, limiting their speed and power efficiency. Photonics could be an excellent platform for a hardware implementation of this concept because of its inherent parallelism and unique nonlinear behaviour. We propose using a network of coupled Semiconductor Optical Amplifiers (SOA) and show in simulation that it could be used as a reservoir by comparing it on a benchmark speech recognition task to conventional software implementations. In spite of several differences, they perform as good as or better than conventional implementations. Moreover, a photonic implementation offers the promise of massively parallel information processing with low power and high speed. We will also address the role phase plays on the reservoir performance.

A modular and flexible architecture that realizes a parallel algorithm for real-time image template matching is described. Symmetrically permuted template data (SPTD) are employed in this algorithm to obtain a processing structure with a high degree of parallelism and pipelining, reduce the number of memory accesses to a minimum, and eliminate the use of delay elements that render the dimension of search area to be processed unchangeable. The inherent temporal parallelism and spatial parallelism of the algorithm are fully exploited in developing the hardware architecture. The latter, which is mainly constructed from two types of basic cells, exhibits a high degree of modularity and regularity. The architecture is especially suitable for applications in which adjustments of the dimension of the search area are constantly required. A hardware prototype has been constructed using standard integrated circuits for moving-object detection and interframe motion estimation. It is capable of operating on a search area of size up to 256*256 pixels in real time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Programming with a high degree of parallelism in fortran

Exadata doesn’t have a special way of executing parallel operations that is not available on other platforms running 11gR2 and 12c. However, parallel processing is a key component of Exadata because efficient handling of data warehouse workloads was a primary design goal for Exadata. In addition, because offloading/Smart Scan depends on direct path reads, which can be used by parallel query slaves, parallel operations take on a whole new importance. Traditionally, the efficient use of parallel query has required careful control of concurrency in order to maximize the use of available resources without overwhelming the system. Oracle’s previous attempts at throttling parallel operations to allow them to be used in multiuser environments have not been entirely successful. Version 11gR2 provided some new capabilities for controlling parallel operations. In particular, a queueing mechanism has been introduced that allows the number of concurrent parallel processes to be managed more effectively. This approach appears to be much better suited to allowing a high degree of parallelism without overwhelming the available resources than previous attempts. 11gR2 also introduced the ability for Oracle to automatically calculate a degree of parallelism on a statement-by-statement basis. Version 12c introduced a Parallel Statement Queueing enhancement and process memory usage control. Also introduced in version 12c is a Database Resource Manager (DBRM) directive which allows the critical queries to bypass the parallel statement queue, and a new database parameter that limits the total Program Global Area (PGA) size, for which the idea is to avoid excessive physical memory usage that leads to high rates of swapping.

Computer Network Integrated Manufacturing: Performance Evaluation Using Distributed Simulation

The next milestone objective of HPC is exascale computing, which includes millions of nodes in the system. One of the key critical barrier toward realizing exascale computing is the fundamental challenge of communication networks. We propose a high performance optical interconnect architecture based on Arrayed waveguide grating router (AWGR) with WDM wavelength routing, the inherent parallelism in AWGRs and multi-hop switching provide high scalability of the network. Theoretical analysis and simulation show its better performance compared with fat-tree architecture.

To increase the scanning speed of cone-beam CT, a scanning configuration with three pairs of x-ray sources and panel detectors was proposed. In this paper, we apply the M-line-based backprojected filtration algorithm to this scanning configuration and propose a fast implementation for this algorithm. Compared with existing implementations, the advantages of our implementation are as follows: (1) it can directly reconstruct horizontal slices (i.e. the slices perpendicular to the rotation axis), without 3D interpolation; (2) it does not need to calculate the backprojection intervals for any point; (3) it has a high degree of parallelism and is suitable for acceleration on graphic processing units or other parallel systems.

B1 subdivisions are narrow foliated zones of stubby, skeletal olivine blades, situated at the top of the granular olivine cumulates (B2) in ponded komatiite lavas. They developed at a late stage in pond crystallization as a result of compaction-related circulation of intercumulus liquids through and along the top of the cumulates. The total thickness of a B1 and its degree of blade parallelism are related to lateral position within ponded lavas. The deeper, hotter and longer-lived core regions generated a thick B1 with a high degree of blade parallelism (ordered B1), whereas the shallower, peripheral regions produced a narrow B1 with a poor degree of blade parallelism (disordered B1), or failed to develop one at all.

SummaryA parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time.

Distributed simulation using a network of processors

Distributed simulation of activity networks

The STI Cell Broadband Engine (BE) is a highly capable heterogeneous multicore processor with large bandwidth and computing power perfectly suited for numerical simulation. However, all performance benefits come at the price of productivity since more responsibility is put to the programmer. In particular, programming with the IBM Cell SDK is hampered by not only taking care of a parallel decomposition of the problem but also of managing all data transfers and organizing all computations in a performance-beneficial manner. While raising complexity of program development, this approach enables efficient utilization of available resources.In the present work we investigate the potential and the performance behavior of Cell’s parallel cores for a resource-demanding and bandwidth-bound multigrid solver for a three-dimensional Poisson problem. The chosen multigrid method based on a parallel Gauß-Seidel and Jacobi smoothers combines mathematical optimality with a high degree of inherent parallelism. We investigate dedicated code optimization strategies on the Cell platform and evaluate associated performance benefits by a comprehensive analysis. Our results show that the Cell BE platform can give tremendous benefits for numerical simulation based on well-structured data. However, it is inescapable that isolated, vendor-specific, but performance-optimal programming approaches need to be replaced by portable and generic concepts like OpenCL – maybe at the price of performance loss.KeywordsCell BEIBM Cell SDKmultigridGauß-Seidel smootherstencil kernelperformance analysis

The rise of artificial intelligence (AI) has driven increasingly stringent requirements for computing speed and energy efficiency. Optical computing offers a promising alternative due to its inherent parallelism and low power consumption. Optical neural networks (ONNs), as an actively studied application of optical computing in AI, have shown potential in matrix operations and neural network inference. However, existing ONNs remain constrained by limited diversity of network layers and an insufficient number of tunable weights. Here, we propose the PCM-MD (phase-change-materials-microring-diffraction) hybrid ONN architecture based on microring resonators, diffraction slots, and phase-change materials that enables diverse optical parameterized layers. The architecture features 679 tunable weights distributed across convolutional, nonlinear, compression, and fully connected layers. PCM-MD demonstrates its effectiveness across multiple intelligent tasks, achieving 85.12% accuracy on Fashion-MNIST classification, 100% accuracy on 3-bit arithmetic addition, and enabling content generation by serving as both generator and discriminator in optical generative adversarial networks (GANs). This optical parameterized architecture provides a promising foundation for energy-efficient AI systems.

We propose an AWGR and SOA based scalable optical packet switch architecture with modular structure and highly distributed control scheme for data center networks. Numerical results show this architecture can achieve high throughput with low blocking probability and latency.