- Conference Article
4
- 10.1109/eiconrus.2019.8657151
Features of the Design Operating Unit Inference Engine and Its Implementation on FPGA
- Jan 01, 2019
- Alexey S Kuvaev + 2 more +2
Modern information technologies are increasingly focused on the tasks related to the knowledge processing: intelligent Internet search systems and enterprise resource planning, DataMining and smart home systems, recommender systems for various purposes, etc. Such problems are specified by the availability of large arrays of complexly structured symbol information, a high degree of implicit parallelism, weak formalizability, and a low need for complex arithmetic operations. As a result, the solution of such problems using the off-the-shelf microprocessors is extremely inefficient. One of approaches to solving this problem is to develop a specialized hardware device designed for high-performance symbolic data processing. The proposed logical inference engine is focused on the accelerated method of parallel logical inference that has a high degree of parallelism, and dataflow architecture. The article describes the development of the executive processor of the logical inference engine. The emphasize is placed on the unification unit design. A new method of parallel unification of the predicate pairs is presented. The unification unit logic diagrams developed using the Quartus CAD system have been implemented on FPGA by Altera. The comparative analysis of the sequential and parallel unit implementation on the basis of the experiments performed is provided.
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