A probabilistic analysis technique for single event transient sensitivity evaluation of phase-lock-loops

Single event transients (SETs) stand out as one of the major causes of soft errors in nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in the design of radiation-hard integrated circuits, the cost-effective approaches for characterization and modeling of SET generation effects in standard logic cells are required. In this work, a SPICE-based methodology for characterization of SET generation effects, employing two different SET current models, is presented. Based on the acquired simulation results, the empirical models for the two main SET generation metrics (SET critical charge and SET pulse width) are derived. The SET generation models and the respective model parameters are intended to be used as inputs for the higher-level analysis of SET effects in digital circuits designed with the characterized standard logic cells. By storing the model parameters for each gate in the look-up table, instead of storing the raw data obtained from SPICE simulations, the amount of characterization data can be significantly reduced, allowing to speed up the subsequent SET analysis of a complex circuit.

A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-μm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.

Single event upset mitigation by means of a sequential circuit state freeze

Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients (SET) that come from the upstream combinational circuits and propagate to the data inputs of flip-flops near the capturing clock edge. This paper presents a SET suppressor that can mitigate such SETs. By adjusting the clock edge timing so that the flip-flop captures data when the data returns to a correct state, the SET suppressor protects a flip-flop against SETs. The clock edge timing adjustment results in flip-flop delay. However, the SET suppressor almost does not introduce flip-flop delay when no SET occurs near the capturing clock edge, which is a great majority of time.

Estimating the frequency of the elements in a data set is commonly needed in data analysis. With the increase of the size of the data sets, accurately computing the number of times that each element appears with a counter becomes impractical. Instead, the Count Min Sketch (CMS) is widely used in big data processing to estimate frequency due to its simplicity and small storage needs. However, soft errors caused by Single Event Transients (SETs) will affect the hardware implementation of the CMS, mainly the hash functions. In this paper, the effect of SETs on the hash functions of the CMS frequency estimate is analyzed theoretically in terms of overestimation probability, underestimation probability, and the equal probability, and further discussed for data with different frequency. Simulation results verify the correctness of the theoretical analysis and reveal several valuable conclusions. First, a large portion of SETs can be tolerated by the CMS itself, and the reliability of the CMS improves when larger number of arrays are used. Second, the average probability for overestimation and underestimation are almost the same, and decrease for larger numbers of arrays. Third, SETs are more likely to cause underestimation for the most frequent data elements. Finally, the overall effect of SETs on the CMS is slightly affected by the number of counters in each array, and seems to be independent of the distribution of the input sequence. The results and analysis presented in this paper provide a starting point for the design of efficient SET fault-tolerant schemes for the CMS.

A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

Model and analysis of single event transient sensitivity based on uncertainty quantification

The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology, thus affecting the propagated single event transient (SET) pulsewidths in circuits. The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range. The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current, and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.

We compare and report in this work heavy-ion irradiation induced single event transients (SETs) in sub-10nm node SOI multiple gate FETs with the help of calibrated 3-D TCAD simulations. Our analysis includes the nanosheet FET (NSFET), nanowire FET (NWFET), and FinFET along with two different device design modes based on the doping profiles, namely the inversion (INV) and junctionless mode (JL). We have also analyzed the impact of heavy-ion strike direction and angle of incidence on SET performance of various MuGFETs. Heavy-ion induced SET current has also been compared for multiple-sheet/wires of NSFET and NWFET. In addition to this, different locations of heavy-ion strike have also been considered in this work. Further, we have collated the simulation trends to propose empirical models that predict the impact of heavy-ion radiation on various MuGFETs. Our models include some of the device design parameters and heavy-ion exposure conditions as the input to the model. The proposed models are shown to correlate well with the TCAD simulation results for the set of model parameters that we have reported here. These models not only expedite the analysis, but these can also accurately predict SETs in advanced MuGFETs under heavy-ion irradiation.

As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.

This article describes a method to detect and classify single-event transients (SETs) to determine the originating circuit node impacted by ionizing radiation. SETs were measured via two-photon absorption (TPA) laser excitation on a custom CMOS phase-locked loop (PLL), and convolutional neural networks (CNNs) were used to classify the spatial dependencies of the transient responses. A clustering technique is described to identify the groups of related circuit nodes and achieves over 90% identification accuracy.

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with clock inputs driven by an inverter chain. The test structure was irradiated with ions at linear energy transfers (LETs) of 4.0, 5.6, 10.4, and 17.9 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, and the cross sections of SET pulses measured down to 12.7 ps are presented. The experimental results are interpreted using a modeling methodology that combines TCAD and radiation effect simulations to capture the SET physics, and SPICE simulations to model the SETs in a circuit. The modeling shows that only ion strikes on the fin structure of the transistor would result in enough charge collected to produce SETs, while strikes in the subfin and substrate do not result in enough charge collected to produce measurable transients. Comparisons of the cumulative cross sections obtained from the experiment and from the simulations validate the modeling methodology presented.

Single-event transients (SET) are analyzed in integer- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> frequency dividers configured internal and external to a closed-loop phase-locked loop (PLL) circuit. Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strongly influence both the error rate of the PLL circuit and the propagation of transients through the closed-loop. The probability of an ion-strike causing output phase displacement values on the order of the operating-period can be significantly reduced by increasing the divisor of the stand-alone output frequency divider. Conversely, increasing the feedback divisor is shown to magnify SETs propagating through the closed-loop PLL.

Single event transient (SET) issues become a primary concern in modern CMOS logic circuits. The possibility of soft errors due to the propagation of SETs is increasing, and becomes a significant reliability challenge. In this paper, single event transients in a 100 series 0.18 μm partially-depleted Silicon-On-Insulator (PDSOI) CMOS inverter chain are studied by pulsed laser. Through experiment, the propagation-induced pulse broadening (PIPB) effect is observed. PIPB is mainly caused by float-body-induced threshold voltage hysteresis in PDSOI transistors. And, it is found that SET pulses don't reach rail-to-rail swings, because of voltage dividing between internal resistance of oscilloscope and on resistance of PMOSFET.