A PVT-Tolerant, Curvature-Compensated CMOS Bandgap-Based Current Reference With Single-Point Batch Trim

A new 1-V high precision second-order compensated bandgap voltage reference (BGR) is presented in this paper. It utilizes a conventional first-order current-mode BGR to balance the Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT with a Proportional to Absolute Temperature (PTAT) voltage. The residual second-order error is corrected by the difference of two CTAT voltages with different non-linear terms through control of the collector currents of BJTs. All the circuits are designed using a standard 0.18μm CMOS process. The post-simulation results show that the maximum temperature coefficient (TC) of the proposed BGR at 1 V power supply is 2.5 ppm/°C over temperature range of −40 °C to 125 °C. The line regulation is 0.23 mV/V over supply range of 0.9 V–2 V. The low frequency power supply rejection of the circuit is −53 dB at 1 V power supply.

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

A new sub-1-ppm/°C curvature-compensated bandgap voltage reference (BGR) is presented in this paper. The Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT is first well balanced with a Proportional to Absolute Temperature (PTAT) voltage, leaving only a high order logarithmic error with the form of TlnT. This residual non-linear error is corrected by a difference of two CTAT voltages with different non-linear terms through controlling the collector currents of BJTs, which can achieve an ideal non-linear compensation. All the circuits are designed in a standard 0.35-pm CMOS process. The post-simulation results show the proposed BGR achieves temperature coefficient (TC) of 0.7 ppm/°C over temperature range of −40 °C to 125 °C and power supply rejection (PSR) of −104 dB at 3.6 V power supply. The line regulation of the output reference voltage is 0.1 mV/V in the supply range of 24.5 V. The maximum dissipating current from the supply is 25.45 μA.

Two original superior-order curvature-corrected voltage references was presented. In order to improve the temperature behavior of the circuits, double differential structures was used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary to absolute temperature) voltage generator was proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference. The superior-order curvature-correction was implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (proportional to absolute temperature) and PTAT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The SPICE simulations confirm the theoretical estimated results, showing temperature coefficients under 11 ppm/K for an extended input range 173K < T < 423K and for a supply voltage of 2.5V and a current consumption of about 1muA

A chip-area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated ΔV GS of NMOS transistors is proposed in this paper. The ΔV GS of two different-V th NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary -to-absolute-temperature (CTAT) and proportional-to-absolute- temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC ΔV GS to a diode-connected NMOS and provide the low-TC V REF . Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-μm CMOS process. An average TC of 27.26 ppm/°C is measured across 6 dies with a standard derivation of 16.40 ppm/°C over −40 to 80 °C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than −62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm2.

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

An on-chip crystal-less relaxation oscillator is presented in this work. It exhibits a self-biased current reference to reduce the overall supply voltage sensitivity in which the input current is made to directly depend on the output current of the current source itself instead of having an input current connected directly to the supply voltage. The temperature compensation is achieved from bipolar bandgap topology in order to take advantage of summing the proportional-to-absolute-temperature (PTAT) current and the complementary-to-absolute-temperature (CTAT) current. Through carefully sized output transistors, a drain current IREF is generated to charge and discharge the oscillating capacitor. This design demonstrates a simple compensation technique that achieves a frequency variation of less than ±1% with a supply voltage of 1.8V input at normal temperature. A linear regulation performance achieves less than ±1% over supply voltage that ranges from 1.62V to 1.98V. A temperature coefficient less than 200ppm/°C is achieved over the temperature range of -10 to 120°C. The whole chip occupies 0.57mm2 (753.3 μm x 753.3 μm) and consumes 700 μW. This oscillator has been designed and analyzed with 0.18μm 1p6m TSMC CMOS process, intended to serve as a clock generator of power electronic systems to improve worst-case power efficiency.

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption [1], BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD/(n·VT)</sup> to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.

A voltage reference circuit is an essential block of a system to generate various internal voltages. Since it consumes static power in standby modes, it plays an important role in energy management of battery-limited applications. The bandgap reference (BGR) has been a widely used approach since it provides a well-defined large value ($\sim 1.15\text{V}$) with strong immunity to process, supply and temperature changes. Recently proposed BGR approaches achieved a great reduction of power consumption by taking only complementary-to-absolute-temperature (CTAT) quantity from a PN junction while they obtained proportional-to-absolute-temperature (PTAT) quantity from alternative CMOS circuits such as a CTAT divider [1]or leakage-based two diodes [2, 3]. However, these BGR schemes are formed with multiple branches fed from a supply voltage above 1.4V and require power consumption of order larger than 10nW. To further reduce power consumption, threshold-based reference approaches with CMOS-only circuits have been proposed [4, 5]. However, generation of a practical voltage level by up-scaling of a threshold-based reference also causes an amplification of the uncertainty by the same factor. I addition, though [4]has successfully achieved sub-nW power consumption, the threshold voltage eventually suffers from a large sensitivity to process variation because the threshold voltage is affected by process and design parameters. To reduce the effect of process variation, [5]proposed a PMOS-only circuit. However, it requires a different body biasing for a threshold difference that is needed to generate a non-zero reference.

This work presents a technique for temperature compensation of Silicon Piezoresistive Pressure Sensors (PPSs) based on a Proportional to Absolute Temperature (PTAT) Bias-Current circuit (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PTAT</sub> ). This technique is applied on the Multi-Stage Current-Mode Piezoresistive Pressure Sensor based on a 3-Terminal Pressure Sensor (3-TPS) that recently has been being studied as an alternative to the conventional Wheatstone Bridge and Transversal PPSs. The experimental maximum differential sensitivity of the sensor output current relative change, for 500μA constant bias current, amounts to 0.64%/psi @20°C. The sensor output current sensitivity temperature dependence, without compensation, amounts to 0.06μA/°C over a range from 20°C to 80°C. After compensation, the experimental results show a maximum deviation of 1.5% within the full scale output span. This efficient compensation was achieved using a PTAT bias current whose Temperature Coefficient (TC) amounts to 0.06μA/°C.

The ring oscillator (RO) is applied to many modern circuits given its simplicity, low-area-cost, low-power. However, the temperature-drifting propagation delay of logic gates makes the RO a difficult solution for frequency reference design in deep submicron process. This work presents the design and implementation of a temperature self-compensation architecture based on a balanced hybrid ring oscillator (BHRO) for precise temperature compensation and clock-on-chip applications. The proposed BHRO is formed by both PTAT (proportional to the absolute temperature) and CTAT (complementary to absolute temperature) delay cells to implements RO-internal compensation. The features include temperature-self-compensation, process insensitive and low-area-cost. Four different test chips are fabricated in the 0.13μm CMOS process. The measurement result exhibits two performance-friendly BHRO architectures with a best temperature coefficient of 31 ppm/C over -55 to 80 , which is among the lowest to our best knowledge. The output compensated frequency is verified to be adjustable varying from 6.95 MHz to 26.5MHz, which are the highest as we have known.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.