Superior-Order Curvature-Corrected Voltage References Using Double Differential Structures

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original CTAT (complementary with absolute temperature) voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy. The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PPAT (proportional with absolute temperature) and PTAT/sup 2/. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the zero-order compensated voltage reference, will be replaced by a DTMOS (dynamic threshold MOS) transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 9.4 ppm/K for an extended input range 173 K < T < 423K and for a supply voltage of 2.5V and a current consumption of about 1/spl mu/A.

Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<10 μA). This work addresses these shortcomings by generating a complementary to absolute temperature (CTAT) current that reproduces the temperature dependence of the proportional to absolute temperature (PTAT) current including its curvature over process corners, eliminating multi-temperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-μA to single-digit μA range. To validate the proposed approach, we fabricated a prototype design in a 130nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6V to 3V. Measurements from 10 chips yield a mean current of 1.1 μA (σ/μ ≈ 4.4%) close to the design target of 1.2 μA. Experimental results further demonstrate an average TC of 110 ppm/∘C from 0 ∘C to 100 ∘C without multi-temperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.

A new 1-V high precision second-order compensated bandgap voltage reference (BGR) is presented in this paper. It utilizes a conventional first-order current-mode BGR to balance the Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT with a Proportional to Absolute Temperature (PTAT) voltage. The residual second-order error is corrected by the difference of two CTAT voltages with different non-linear terms through control of the collector currents of BJTs. All the circuits are designed using a standard 0.18μm CMOS process. The post-simulation results show that the maximum temperature coefficient (TC) of the proposed BGR at 1 V power supply is 2.5 ppm/°C over temperature range of −40 °C to 125 °C. The line regulation is 0.23 mV/V over supply range of 0.9 V–2 V. The low frequency power supply rejection of the circuit is −53 dB at 1 V power supply.

A new sub-1-ppm/°C curvature-compensated bandgap voltage reference (BGR) is presented in this paper. The Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT is first well balanced with a Proportional to Absolute Temperature (PTAT) voltage, leaving only a high order logarithmic error with the form of TlnT. This residual non-linear error is corrected by a difference of two CTAT voltages with different non-linear terms through controlling the collector currents of BJTs, which can achieve an ideal non-linear compensation. All the circuits are designed in a standard 0.35-pm CMOS process. The post-simulation results show the proposed BGR achieves temperature coefficient (TC) of 0.7 ppm/°C over temperature range of −40 °C to 125 °C and power supply rejection (PSR) of −104 dB at 3.6 V power supply. The line regulation of the output reference voltage is 0.1 mV/V in the supply range of 24.5 V. The maximum dissipating current from the supply is 25.45 μA.

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

ABSTRACTThis paper proposes a nanowatt voltage reference (VR) with temperature coefficient compensation. All transistors work in the subthreshold region. The complementary‐to‐absolute‐temperature (CTAT) voltage and proportional‐to‐absolute‐temperature (PTAT) voltage are mainly generated by two NMOS transistors with different threshold voltages. At the same time, a simple temperature compensation circuit is designed to optimize the temperature coefficient at high temperatures, so that the proposed VR circuit can generate a reference voltage with a wider temperature range and a lower temperature coefficient. The proposed VR circuit is implemented using a standard 0.18‐μm CMOS process with an active area of only 0.022 mm2. The postlayout simulation results show that the proposed VR circuit generates a reference voltage of 308.21 mV at room temperature. Its temperature coefficient is 6.4 ppm/°C over a temperature range of −40°C°C–140°C, with a power consumption of 7.4 nW. The voltage line sensitivity (LS) is 0.098%/V, and the power supply ripple rejection (PSRR) is −72 dB @DC and −42 dB @10 MHz.

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

A chip-area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated ΔV GS of NMOS transistors is proposed in this paper. The ΔV GS of two different-V th NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary -to-absolute-temperature (CTAT) and proportional-to-absolute- temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC ΔV GS to a diode-connected NMOS and provide the low-TC V REF . Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-μm CMOS process. An average TC of 27.26 ppm/°C is measured across 6 dies with a standard derivation of 16.40 ppm/°C over −40 to 80 °C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than −62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm2.

SummaryVoltage references are typically designed by combining a complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltage references. However, in contrast to conventional voltage references, the proposed circuit generates a voltage reference by subtracting two PTAT voltages, resulting in an extremely low process‐dependent voltage reference. A novel subtractor is also proposed for subtracting PTAT voltages, which is used to generate the reference voltage. The temperature coefficient of the proposed voltage reference is further improved using a novel PTAT slope compensation technique. The proposed voltage reference is a MOS‐only ultra‐low power circuit that works with sub‐bandgap supply voltage. Simulation results using UMC 0.18 m technology MOSFETs show that the proposed circuit has a line sensitivity of 0.5%/V, a temperature coefficient of 21.37 ppm/° C, a power consumption of 15.6 nW, and an output voltage variation of only 0.22% due to process variations.

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption [1], BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD/(n·VT)</sup> to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.

High linear voltage reference circuitry is designed and implemented in TSMC 0.13 mum and 0.18 mum CMOS technology. Previous research has proposed the use of MOS transistors operating in the weak inversion region to replace the bipolar devices in conventional PTAT (proportional to absolute temperature) circuits. However, such solutions often have linearity problem in high temperature region due to the current leaking devices in modern deep sub micron and nano-scale CMOS technology. The proposed circuit utilized temperature complementation technique on two voltage references, PTAT and IOAT (independent of absolute temperature) references, to enhance the linearity and produce a more stable lOAT voltage reference. Base on the simulation results, the R-squares of both circuitries are better than 0.999 in a considerable wider temperature range from -55degC to 170degC. Thus, a fully integrated temperature sensor with wider temperature range is designed and easily to integrate to modern system-on-chip designs with minimal efforts.